[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20230309143551.200694-2-brgl@bgdev.pl>
Date: Thu, 9 Mar 2023 15:35:50 +0100
From: Bartosz Golaszewski <brgl@...ev.pl>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
Subject: [PATCH 1/2] arm64: dts: sm8150: add the QUPv3 high-speed UART node
From: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
Add the high-speed UART node to the dtsi for sm8150.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 13e0ce828606..cd0351a33516 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1334,6 +1334,20 @@ spi9: spi@...000 {
status = "disabled";
};
+ uart9: serial@...000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00a84000 0x0 0x4000>;
+ reg-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_uart9_default>;
+ pinctrl-names = "default";
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
i2c10: i2c@...000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a88000 0 0x4000>;
@@ -2425,6 +2439,13 @@ qup_spi9_default: qup-spi9-default-state {
bias-disable;
};
+ qup_uart9_default: qup-uart9-default-state {
+ pins = "gpio41", "gpio42";
+ function = "qup9";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
qup_i2c10_default: qup-i2c10-default-state {
pins = "gpio9", "gpio10";
function = "qup10";
--
2.37.2
Powered by blists - more mailing lists