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Message-ID: <20230310092804.692303-2-s-vadapalli@ti.com>
Date: Fri, 10 Mar 2023 14:58:03 +0530
From: Siddharth Vadapalli <s-vadapalli@...com>
To: <nm@...com>, <vigneshr@...com>, <kristo@...nel.org>,
<robh+dt@...nel.org>, <krzysztof.kozlowski@...aro.org>,
<krzysztof.kozlowski+dt@...aro.org>
CC: <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <srk@...com>,
<s-vadapalli@...com>
Subject: [PATCH 1/2] arm64: dts: ti: k3-j721e: Add CPSW9G nodes
TI's J721E SoC has a 9 port Ethernet Switch instance with 8 external
ports and 1 host port, referred to as CPSW9G.
Add device-tree nodes for CPSW9G and disable it by default. Device-tree
overlays will be used to enable it.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@...com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 107 ++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 +
2 files changed, 108 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index c935622f0102..1ac7a47fc437 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -61,6 +61,13 @@ serdes_ln_ctrl: mux-controller@...0 {
<J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};
+ cpsw0_phy_gmii_sel: phy@...4 {
+ compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
+ ti,qsgmii-main-ports = <2>, <2>;
+ reg = <0x4044 0x20>;
+ #phy-cells = <1>;
+ };
+
usb_serdes_mux: mux-controller@...0 {
compatible = "mmio-mux";
#mux-control-cells = <1>;
@@ -404,6 +411,106 @@ cpts@...d0000 {
};
};
+ cpsw0: ethernet@...0000 {
+ compatible = "ti,j721e-cpswxg-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0xc000000 0x0 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>;
+ clocks = <&k3_clks 19 89>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&main_udmap 0xca00>,
+ <&main_udmap 0xca01>,
+ <&main_udmap 0xca02>,
+ <&main_udmap 0xca03>,
+ <&main_udmap 0xca04>,
+ <&main_udmap 0xca05>,
+ <&main_udmap 0xca06>,
+ <&main_udmap 0xca07>,
+ <&main_udmap 0x4a00>;
+ dma-names = "tx0", "tx1", "tx2", "tx3",
+ "tx4", "tx5", "tx6", "tx7",
+ "rx";
+
+ status = "disabled";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpsw0_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ };
+
+ cpsw0_port2: port@2 {
+ reg = <2>;
+ ti,mac-only;
+ label = "port2";
+ };
+
+ cpsw0_port3: port@3 {
+ reg = <3>;
+ ti,mac-only;
+ label = "port3";
+ };
+
+ cpsw0_port4: port@4 {
+ reg = <4>;
+ ti,mac-only;
+ label = "port4";
+ };
+
+ cpsw0_port5: port@5 {
+ reg = <5>;
+ ti,mac-only;
+ label = "port5";
+ };
+
+ cpsw0_port6: port@6 {
+ reg = <6>;
+ ti,mac-only;
+ label = "port6";
+ };
+
+ cpsw0_port7: port@7 {
+ reg = <7>;
+ ti,mac-only;
+ label = "port7";
+ };
+
+ cpsw0_port8: port@8 {
+ reg = <8>;
+ ti,mac-only;
+ label = "port8";
+ };
+ };
+
+ cpsw9g_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x0 0xf00 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 19 89>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ };
+
+ cpts@...00 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x0 0x3d000 0x0 0x400>;
+ clocks = <&k3_clks 19 16>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
main_crypto: crypto@...0000 {
compatible = "ti,j721e-sa2ul";
reg = <0x0 0x4e00000 0x0 0x1200>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index 6975cae644d9..ddbaa06e21bd 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -135,6 +135,7 @@ cbass_main: bus@...000 {
<0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
<0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */
<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
+ <0x00 0x0c000000 0x00 0x0c000000 0x00 0x0d000000>, /* CPSW9G */
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/
--
2.25.1
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