linux-kernel - Re: [PATCH 09/15] arm64: dts: qcom: sm6375: Add CPUCP L3 node

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Message-ID: <4390532c-cf94-0030-8997-1a3522272f4f@linaro.org>
Date:   Fri, 10 Mar 2023 14:15:12 +0100
From:   Konrad Dybcio <konrad.dybcio@...aro.org>
To:     Sibi Sankar <quic_sibis@...cinc.com>,
        Amit Kucheria <amitk@...nel.org>,
        Thara Gopinath <thara.gopinath@...il.com>,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        "Rafael J. Wysocki" <rafael@...nel.org>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Zhang Rui <rui.zhang@...el.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Georgi Djakov <djakov@...nel.org>
Cc:     linux-arm-msm@...r.kernel.org, linux-pm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 09/15] arm64: dts: qcom: sm6375: Add CPUCP L3 node



On 10.03.2023 04:14, Sibi Sankar wrote:
> Hey Konrad,
> 
> Thanks for the patch.
> 
> On 3/4/23 03:28, Konrad Dybcio wrote:
>> Enable the CPUCP block responsible for scaling the L3 cache.
> 
> FWIW, the patch just enables the l3 provider, the CPUCP block would
> already be up at this point. You would also want to include the
> expansion for CPUCP at least once in your patch.
Right, I didn't think much about this, but I should probably reword
this and the bindings commit to mention that CPUCP != L3 scaler within.

Konrad
> 
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
> 
> Reviewed-by: Sibi Sankar <quic_sibis@...cinc.com>
> 
>> ---
>>   arch/arm64/boot/dts/qcom/sm6375.dtsi | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi
>> index 90f18754a63b..59d7ed25aa36 100644
>> --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi
>> @@ -1505,6 +1505,15 @@ frame@...d000 {
>>               };
>>           };
>>   +        cpucp_l3: interconnect@...0000 {
>> +            compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3";
>> +            reg = <0 0x0fd90000 0 0x1000>;
>> +
>> +            clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
>> +            clock-names = "xo", "alternate";
>> +            #interconnect-cells = <1>;
>> +        };
>> +
>>           cpufreq_hw: cpufreq@...1000 {
>>               compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss";
>>               reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>;
>>