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Message-ID: <20230313104721.407071-3-j-choudhary@ti.com>
Date: Mon, 13 Mar 2023 16:17:21 +0530
From: Jayesh Choudhary <j-choudhary@...com>
To: <nm@...com>, <vigneshr@...com>
CC: <kristo@...nel.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <kamlesh@...com>,
<linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<j-choudhary@...com>
Subject: [PATCH 2/2] arm64: dts: ti: k3-j784s4-main: Enable crypto accelerator
Add the node for SA2UL to support hardware crypto algorithms,
including SHA-1/256/512, AES, 3DES and AEAD suites.
Add rng node for hardware random number generator.
Signed-off-by: Jayesh Choudhary <j-choudhary@...com>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 80a1b08c51a8..8c1474a7bd0f 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -72,6 +72,25 @@ main_pmx0: pinctrl@...000 {
pinctrl-single,function-mask = <0xffffffff>;
};
+ main_crypto: crypto@...0000 {
+ compatible = "ti,j721e-sa2ul";
+ reg = <0x00 0x4e00000 0x00 0x1200>;
+ power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
+
+ dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
+ <&main_udmap 0x4a41>;
+ dma-names = "tx", "rx1", "rx2";
+
+ rng: rng@...0000 {
+ compatible = "inside-secure,safexcel-eip76";
+ reg = <0x00 0x4e10000 0x00 0x7d>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
main_uart0: serial@...0000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x200>;
--
2.25.1
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