linux-kernel - [PATCH v2] arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller

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Message-Id: <20230313125731.17745-1-quic_kbajaj@quicinc.com>
Date:   Mon, 13 Mar 2023 18:27:31 +0530
From:   Komal Bajaj <quic_kbajaj@...cinc.com>
To:     Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc:     Komal Bajaj <quic_kbajaj@...cinc.com>,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: [PATCH v2] arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller

Add a DT node for Last level cache (aka. system cache) controller
which provides control over the last level cache present on QDU1000
and QRU1000 SoCs.

Changes in v2:
  - Addressing comments from Konrad.

Signed-off-by: Komal Bajaj <quic_kbajaj@...cinc.com>
---
 arch/arm64/boot/dts/qcom/qdu1000.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index f234159d2060..911ade2faa19 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -1320,6 +1320,18 @@ gem_noc: interconnect@...00000 {
 			qcom,bcm-voters = <&apps_bcm_voter>;
 			#interconnect-cells = <2>;
 		};
+
+		system-cache-controller@...00000 {
+			compatible = "qcom,qdu1000-llcc";
+			reg = <0 0x19200000 0 0xd80000>,
+			      <0 0x1a200000 0 0x80000>,
+			      <0 0x221c8128 0 0x4>;
+			reg-names = "llcc_base",
+				    "llcc_broadcast_base",
+				    "multi_channel_register";
+			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+			multi-ch-bit-off = <24 2>;
+		};
 	};
 
 	timer {
-- 
2.39.1