[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <3a91a794-b56e-eb21-58da-5abc8edbbc37@redhat.com>
Date: Mon, 13 Mar 2023 16:03:08 +0100
From: Hans de Goede <hdegoede@...hat.com>
To: Jithu Joseph <jithu.joseph@...el.com>, markgross@...nel.org
Cc: tglx@...utronix.de, mingo@...hat.com, bp@...en8.de,
dave.hansen@...ux.intel.com, x86@...nel.org, hpa@...or.com,
gregkh@...uxfoundation.org, rostedt@...dmis.org,
ashok.raj@...el.com, tony.luck@...el.com,
linux-kernel@...r.kernel.org, platform-driver-x86@...r.kernel.org,
patches@...ts.linux.dev, ravi.v.shankar@...el.com,
thiago.macieira@...el.com, athenas.jimenez.gonzalez@...el.com,
sohil.mehta@...el.com
Subject: Re: [PATCH v3 3/8] x86/include/asm/msr-index.h: Add IFS Array test
bits
Hi,
On 3/1/23 02:59, Jithu Joseph wrote:
> Define MSR bitfields for enumerating support for Array BIST test.
>
> Signed-off-by: Jithu Joseph <jithu.joseph@...el.com>
> Reviewed-by: Tony Luck <tony.luck@...el.com>
> ---
> arch/x86/include/asm/msr-index.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index d3fe82c5d6b6..ad8997773ad3 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -197,6 +197,8 @@
>
> /* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */
> #define MSR_INTEGRITY_CAPS 0x000002d9
> +#define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2
> +#define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT)
> #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4
> #define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT)
>
Thanks, patch looks good to me:
Reviewed-by: Hans de Goede <hdegoede@...hat.com>
Regards,
Hans
Powered by blists - more mailing lists