linux-kernel - RE: [RFC] clk: imx: Let IMX8MN_CLK_DISP

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Message-ID: <DU0PR04MB9417C49457C9E60898E6A92188BE9@DU0PR04MB9417.eurprd04.prod.outlook.com>
Date:   Tue, 14 Mar 2023 04:39:24 +0000
From:   Peng Fan <peng.fan@....com>
To:     Adam Ford <aford173@...il.com>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>
CC:     "l.stach@...gutronix.de" <l.stach@...gutronix.de>,
        Abel Vesa <abelvesa@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        Fabio Estevam <festevam@...il.com>,
        dl-linux-imx <linux-imx@....com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [RFC] clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate

> Subject: [RFC] clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate
> 
> By default the display pixel clock needs to be evenly divide down from
> 594MHz which rules out a significant number of resolution and refresh rates.
> The current clock tree looks something like:
> 
>  video_pll                594000000
>   video_pll_bypass        594000000
>    video_pll_out          594000000
>     disp_pixel            148500000
>      disp_pixel_clk       148500000
> 
> To enable CLK_SET_RATE_PARENT on disp_pixel, a helper function needs to
> be added called imx8m_clk_hw_composite_flags which can pass the
> additional flag to the clock controller. Letting disp_pixel set video_pll_out
> rate should actually lower the clock rates of video_pll_bypass and video_pll
> as well, since those clocks are already configured to enable
> CLK_SET_RATE_PARENT.
> 
> Signed-off-by: Adam Ford <aford173@...il.com>
> ---
> 
> This is an RFC, because even with this patch, the video_pll_out clock does
> not drop to 148500000 like I would expect.  The video_pll clock is a
> fractional pll, so it should be able to generate a significant number of
> optional clock frequencies to facilitate video.
[Peng Fan] 

Have you ever tried to directly set video pll out clk to the freq that you wanna?

Regards,
Peng.

> 
> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
> index af256ade554f..a116cc40d7d0 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -470,7 +470,7 @@ static int imx8mn_clocks_probe(struct
> platform_device *pdev)
>  	hws[IMX8MN_CLK_DRAM_ALT] =
> imx8m_clk_hw_fw_managed_composite("dram_alt",
> imx8mn_dram_alt_sels, base + 0xa000);
>  	hws[IMX8MN_CLK_DRAM_APB] =
> imx8m_clk_hw_fw_managed_composite_critical("dram_apb",
> imx8mn_dram_apb_sels, base + 0xa080);
> 
> -	hws[IMX8MN_CLK_DISP_PIXEL] =
> imx8m_clk_hw_composite("disp_pixel", imx8mn_disp_pixel_sels, base +
> 0xa500);
> +	hws[IMX8MN_CLK_DISP_PIXEL] =
> +imx8m_clk_hw_composite_flags("disp_pixel", imx8mn_disp_pixel_sels,
> base
> ++ 0xa500, CLK_SET_RATE_PARENT);
>  	hws[IMX8MN_CLK_SAI2] = imx8m_clk_hw_composite("sai2",
> imx8mn_sai2_sels, base + 0xa600);
>  	hws[IMX8MN_CLK_SAI3] = imx8m_clk_hw_composite("sai3",
> imx8mn_sai3_sels, base + 0xa680);
>  	hws[IMX8MN_CLK_SAI5] = imx8m_clk_hw_composite("sai5",
> imx8mn_sai5_sels, base + 0xa780); diff --git a/drivers/clk/imx/clk.h
> b/drivers/clk/imx/clk.h index 689b3ad927c0..9977b512845b 100644
> --- a/drivers/clk/imx/clk.h
> +++ b/drivers/clk/imx/clk.h
> @@ -414,6 +414,10 @@ struct clk_hw *__imx8m_clk_hw_composite(const
> char *name,
>  	_imx8m_clk_hw_composite(name, parent_names, reg, \
>  			0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
> 
> +#define imx8m_clk_hw_composite_flags(name, parent_names, reg, flags)
> \
> +	_imx8m_clk_hw_composite(name, parent_names, reg, \
> +			0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT |  flags)
> +
>  #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \
>  	_imx8m_clk_hw_composite(name, parent_names, reg, \
>  			0, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
> --
> 2.37.2