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Message-Id: <20230314102410.424773-11-dev@pschenker.ch>
Date:   Tue, 14 Mar 2023 11:23:56 +0100
From:   Philippe Schenker <dev@...henker.ch>
To:     devicetree@...r.kernel.org, Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>
Cc:     NXP Linux Team <linux-imx@....com>,
        Frank Rowand <frowand.list@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Fabio Estevam <festevam@...il.com>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        linux-arm-kernel@...ts.infradead.org,
        Philippe Schenker <philippe.schenker@...adex.com>,
        linux-kernel@...r.kernel.org
Subject: [PATCH v2 10/23] arm64: dts: colibri-imx8x: Add SPI

From: Philippe Schenker <philippe.schenker@...adex.com>

Add Colibri SPI to the board. lpspi2 is being exposed on the SoM edge.
Add settings to the module-level but finally enable it on the eval-board
dtsi.

Signed-off-by: Philippe Schenker <philippe.schenker@...adex.com>
---

(no changes since v1)

 arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi | 5 +++++
 arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi         | 7 +++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
index dc0339b35a3c..1d0bad085ad4 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
@@ -36,6 +36,11 @@ rtc_i2c: rtc@68 {
 	};
 };
 
+/* Colibri SPI */
+&lpspi2 {
+	status = "okay";
+};
+
 /* Colibri UART_B */
 &lpuart0 {
 	status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index cd7de71c6d73..a2364845e976 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -91,6 +91,13 @@ ethphy0: ethernet-phy@2 {
 	};
 };
 
+/* Colibri SPI */
+&lpspi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpspi2>;
+	cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>;
+};
+
 /* On-module eMMC */
 &usdhc1 {
 	bus-width = <8>;
-- 
2.39.2

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