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Message-ID: <4aff6a7a3b606f26ec793192d9c75774276935e0.camel@mediatek.com>
Date: Wed, 15 Mar 2023 03:45:32 +0000
From: Nancy Lin (林欣螢) <Nancy.Lin@...iatek.com>
To: "p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
"matthias.bgg@...il.com" <matthias.bgg@...il.com>,
"chunkuang.hu@...nel.org" <chunkuang.hu@...nel.org>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"krzysztof.kozlowski+dt@...aro.org"
<krzysztof.kozlowski+dt@...aro.org>
CC: "linux-mediatek@...ts.infradead.org"
<linux-mediatek@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Singo Chang (張興國)
<Singo.Chang@...iatek.com>,
"nathan@...nel.org" <nathan@...nel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"daniel@...ll.ch" <daniel@...ll.ch>,
CK Hu (胡俊光) <ck.hu@...iatek.com>,
"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"clang-built-linux@...glegroups.com"
<clang-built-linux@...glegroups.com>,
"airlied@...ux.ie" <airlied@...ux.ie>,
"ndesaulniers@...gle.com" <ndesaulniers@...gle.com>
Subject: Re: [PATCH v29 1/7] dt-bindings: mediatek: add ethdr definition for
mt8195
On Tue, 2022-12-27 at 16:10 +0800, Nancy.Lin wrote:
> Add vdosys1 ETHDR definition.
>
> Signed-off-by: Nancy.Lin <nancy.lin@...iatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@...nel.org>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@...labora.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> Tested-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@...labora.com>
> ---
> .../display/mediatek/mediatek,ethdr.yaml | 188
> ++++++++++++++++++
> 1 file changed, 188 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yam
> l
>
> diff --git
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
> aml
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
> aml
> new file mode 100644
> index 000000000000..3b11e47a8834
> --- /dev/null
> +++
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
> aml
> @@ -0,0 +1,188 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id:
> http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek Ethdr Device
> +
> +maintainers:
> + - Chun-Kuang Hu <chunkuang.hu@...nel.org>
> + - Philipp Zabel <p.zabel@...gutronix.de>
> +
> +description:
> + ETHDR (ET High Dynamic Range) is a MediaTek internal HDR engine
> and is
> + designed for HDR video and graphics conversion in the external
> display path.
> + It handles multiple HDR input types and performs tone mapping,
> color
> + space/color format conversion, and then combine different layers,
> + output the required HDR or SDR signal to the subsequent display
> path.
> + This engine is composed of two video frontends, two graphic
> frontends,
> + one video backend and a mixer. ETHDR has two DMA function blocks,
> DS and ADL.
> + These two function blocks read the pre-programmed registers from
> DRAM and
> + set them to HW in the v-blanking period.
> +
> +properties:
> + compatible:
> + const: mediatek,mt8195-disp-ethdr
> +
> + reg:
> + maxItems: 7
> +
> + reg-names:
> + items:
> + - const: mixer
> + - const: vdo_fe0
> + - const: vdo_fe1
> + - const: gfx_fe0
> + - const: gfx_fe1
> + - const: vdo_be
> + - const: adl_ds
> +
> + interrupts:
> + maxItems: 1
> +
> + iommus:
> + minItems: 1
> + maxItems: 2
> +
> + clocks:
> + items:
> + - description: mixer clock
> + - description: video frontend 0 clock
> + - description: video frontend 1 clock
> + - description: graphic frontend 0 clock
> + - description: graphic frontend 1 clock
> + - description: video backend clock
> + - description: autodownload and menuload clock
> + - description: video frontend 0 async clock
> + - description: video frontend 1 async clock
> + - description: graphic frontend 0 async clock
> + - description: graphic frontend 1 async clock
> + - description: video backend async clock
> + - description: ethdr top clock
> +
> + clock-names:
> + items:
> + - const: mixer
> + - const: vdo_fe0
> + - const: vdo_fe1
> + - const: gfx_fe0
> + - const: gfx_fe1
> + - const: vdo_be
> + - const: adl_ds
> + - const: vdo_fe0_async
> + - const: vdo_fe1_async
> + - const: gfx_fe0_async
> + - const: gfx_fe1_async
> + - const: vdo_be_async
> + - const: ethdr_top
> +
> + power-domains:
> + maxItems: 1
> +
> + resets:
> + items:
> + - description: video frontend 0 async reset
> + - description: video frontend 1 async reset
> + - description: graphic frontend 0 async reset
> + - description: graphic frontend 1 async reset
> + - description: video backend async reset
> +
> + reset-names:
> + items:
> + - const: vdo_fe0_async
> + - const: vdo_fe1_async
> + - const: gfx_fe0_async
> + - const: gfx_fe1_async
> + - const: vdo_be_async
> +
> + mediatek,gce-client-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: The register of display function block to be set by
> gce.
> + There are 4 arguments in this property, gce node, subsys id,
> offset and
> + register size. The subsys id is defined in the gce header of
> each chips
> + include/dt-bindings/gce/<chip>-gce.h, mapping to the register
> of display
> + function block.
> + items:
> + items:
> + - description: phandle of GCE
> + - description: GCE subsys id
> + - description: register offset
> + - description: register size
> + minItems: 7
> + maxItems: 7
> +
Hi Rob and krzysztof,
I got the two messages when running dt_binding_check [1]. This binding
patch was sent previously in [2].
If I remove the following items/minItems/maxItems in the mediatek,gce-
client property, the two message disappear. I don't know what's wrong
with the original syntax. Do you have any suggestions for this?
- items:
- items:
- - description: phandle of GCE
- - description: GCE subsys id
- - description: register offset
- - description: register size
- minItems: 7
- maxItems: 7
[1].
Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.examp
le.dtb
/proj/mtk19347/cros/src/third_party/kernel/v5.10/Documentation/devicetr
ee/bindings/display/mediatek/mediatek,ethdr.example.dtb:
hdr-engine@...14000: mediatek,gce-client-reg:0: [4294967295, 7, 16384,
4096, 4294967295, 7, 20480, 4096, 4294967295, 7, 28672, 4096,
4294967295, 7, 36864, 4096, 4294967295, 7, 40960, 4096, 4294967295, 7,
45056, 4096, 4294967295, 7, 49152, 4096] is too long
From schema:
/proj/mtk19347/cros/src/third_party/kernel/v5.10/Documentation/devicetr
ee/bindings/display/mediatek/mediatek,ethdr.yaml
/proj/mtk19347/cros/src/third_party/kernel/v5.10/Documentation/devicetr
ee/bindings/display/mediatek/mediatek,ethdr.example.dtb:
hdr-engine@...14000: mediatek,gce-client-reg: [[4294967295, 7, 16384,
4096, 4294967295, 7, 20480, 4096, 4294967295, 7, 28672, 4096,
4294967295, 7, 36864, 4096, 4294967295, 7, 40960, 4096, 4294967295, 7,
45056, 4096, 4294967295, 7, 49152, 4096]] is too short
From schema:
/proj/mtk19347/cros/src/third_party/kernel/v5.10/Documentation/devicetr
ee/bindings/display/mediatek/mediatek,ethdr.yaml
[2] [RESEND,v5,3/3] dt-bindings: mediatek: add ethdr definition for
mt8195
https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20220608043852.4980-4-rex-bc.chen@mediatek.com/
Regards,
Nancy
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - interrupts
> + - power-domains
> + - resets
> + - mediatek,gce-client-reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/mt8195-clk.h>
> + #include <dt-bindings/gce/mt8195-gce.h>
> + #include <dt-bindings/memory/mt8195-memory-port.h>
> + #include <dt-bindings/power/mt8195-power.h>
> + #include <dt-bindings/reset/mt8195-resets.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + hdr-engine@...14000 {
> + compatible = "mediatek,mt8195-disp-ethdr";
> + reg = <0 0x1c114000 0 0x1000>,
> + <0 0x1c115000 0 0x1000>,
> + <0 0x1c117000 0 0x1000>,
> + <0 0x1c119000 0 0x1000>,
> + <0 0x1c11a000 0 0x1000>,
> + <0 0x1c11b000 0 0x1000>,
> + <0 0x1c11c000 0 0x1000>;
> + reg-names = "mixer", "vdo_fe0", "vdo_fe1",
> "gfx_fe0", "gfx_fe1",
> + "vdo_be", "adl_ds";
> + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX
> 0x4000 0x1000>,
> + <&gce0 SUBSYS_1c11XXXX
> 0x5000 0x1000>,
> + <&gce0 SUBSYS_1c11XXXX
> 0x7000 0x1000>,
> + <&gce0 SUBSYS_1c11XXXX
> 0x9000 0x1000>,
> + <&gce0 SUBSYS_1c11XXXX
> 0xa000 0x1000>,
> + <&gce0 SUBSYS_1c11XXXX
> 0xb000 0x1000>,
> + <&gce0 SUBSYS_1c11XXXX
> 0xc000 0x1000>;
> + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
> + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
> + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
> + <&vdosys1 CLK_VDO1_26M_SLOW>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
> + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
> + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
> + <&topckgen CLK_TOP_ETHDR>;
> + clock-names = "mixer", "vdo_fe0", "vdo_fe1",
> "gfx_fe0", "gfx_fe1",
> + "vdo_be", "adl_ds", "vdo_fe0_async",
> "vdo_fe1_async",
> + "gfx_fe0_async",
> "gfx_fe1_async","vdo_be_async",
> + "ethdr_top";
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
> + <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
> + interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /*
> disp mixer */
> + resets = <&vdosys1
> MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
> + <&vdosys1
> MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
> + <&vdosys1
> MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
> + <&vdosys1
> MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
> + <&vdosys1
> MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
> + reset-names = "vdo_fe0_async", "vdo_fe1_async",
> "gfx_fe0_async",
> + "gfx_fe1_async", "vdo_be_async";
> + };
> + };
> +...
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