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Date: Tue, 14 Mar 2023 17:30:17 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Emil Renner Berthing <kernel@...il.dk>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Michael Turquette <mturquette@...libre.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Xingyu Wu <xingyu.wu@...rfivetech.com>,
devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org
Cc: Rob Herring <robh+dt@...nel.org>, Conor Dooley <conor@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Hal Feng <hal.feng@...rfivetech.com>,
Xingyu Wu <xingyu.wu@...rfivetech.com>,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH v3 00/11] Add new partial clock and reset drivers for StarFive JH7110
Quoting Xingyu Wu (2023-03-14 05:43:53)
> This patch serises are to add new partial clock drivers and reset
> supports about System-Top-Group(STG), Image-Signal-Process(ISP)
> and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC.
What is your merge plan for this series? Did you intend for clk tree to
take the majority of patches? We won't take the dts changes through the
clk tree.
I think Philipp Zabel reviewed some earlier version of the patches and
provided reviewed-by tags. Can you check if they can be added here? If
so, please resend again, or get those merged through the reset tree.
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