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Message-ID: <20230315062307.1612220-5-s-vadapalli@ti.com>
Date: Wed, 15 Mar 2023 11:53:07 +0530
From: Siddharth Vadapalli <s-vadapalli@...com>
To: <nm@...com>, <vigneshr@...com>, <kristo@...nel.org>,
<robh+dt@...nel.org>, <krzysztof.kozlowski@...aro.org>,
<krzysztof.kozlowski+dt@...aro.org>, <afd@...com>
CC: <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <srk@...com>,
<s-vadapalli@...com>
Subject: [PATCH v3 4/4] arm64: dts: ti: k3-j7200: Add overlay to enable CPSW5G ports in QSGMII mode
The J7 Quad Port Add-On Ethernet Card for J7200 Common-Proc-Board supports
QSGMII mode. Use the overlay to configure CPSW5G ports in QSGMII mode.
Add support to reset the PHY from kernel by using gpio-hog and gpio-reset.
Add aliases for CPSW5G ports to enable kernel to fetch MAC addresses
directly from U-Boot.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@...com>
---
arch/arm64/boot/dts/ti/Makefile | 3 +-
.../ti/k3-j7200-evm-quad-port-eth-exp.dtso | 100 ++++++++++++++++++
2 files changed, 102 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 7ded6dacd3f2..5312e4adc4e3 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -28,7 +28,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
# Boards with J7200 SoC
-dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb
+k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm.dtb
# Boards with J721e SoC
k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso
new file mode 100644
index 000000000000..78ba7bcedf3f
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
+ * J7200 board.
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mux/ti-serdes.h>
+#include <dt-bindings/pinctrl/k3.h>
+
+&{/} {
+ aliases {
+ ethernet1 = "/bus@...000/ethernet@...0000/ethernet-ports/port@1";
+ ethernet2 = "/bus@...000/ethernet@...0000/ethernet-ports/port@2";
+ ethernet3 = "/bus@...000/ethernet@...0000/ethernet-ports/port@3";
+ ethernet4 = "/bus@...000/ethernet@...0000/ethernet-ports/port@4";
+ };
+};
+
+&cpsw0 {
+ status = "okay";
+};
+
+&cpsw0_port1 {
+ status = "okay";
+ phy-handle = <&cpsw5g_phy0>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 1>;
+};
+
+&cpsw0_port2 {
+ status = "okay";
+ phy-handle = <&cpsw5g_phy1>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 2>;
+};
+
+&cpsw0_port3 {
+ status = "okay";
+ phy-handle = <&cpsw5g_phy2>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 3>;
+};
+
+&cpsw0_port4 {
+ status = "okay";
+ phy-handle = <&cpsw5g_phy3>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 4>;
+};
+
+&cpsw5g_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio0_pins_default>;
+ reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
+ reset-post-delay-us = <120000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw5g_phy0: ethernet-phy@16 {
+ reg = <16>;
+ };
+ cpsw5g_phy1: ethernet-phy@17 {
+ reg = <17>;
+ };
+ cpsw5g_phy2: ethernet-phy@18 {
+ reg = <18>;
+ };
+ cpsw5g_phy3: ethernet-phy@19 {
+ reg = <19>;
+ };
+};
+
+&exp2 {
+ qsgmii-line-hog {
+ gpio-hog;
+ gpios = <16 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "qsgmii-pwrdn-line";
+ };
+};
+
+&main_pmx0 {
+ mdio0_pins_default: mdio0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x00a8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */
+ J721E_IOPAD(0x00a4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */
+ >;
+ };
+};
--
2.25.1
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