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Message-ID: <478974c3-7302-e773-8d70-fcb2323f65ea@linaro.org>
Date: Wed, 15 Mar 2023 08:55:59 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Xingyu Wu <xingyu.wu@...rfivetech.com>,
linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Emil Renner Berthing <kernel@...il.dk>
Cc: Rob Herring <robh+dt@...nel.org>, Conor Dooley <conor@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Hal Feng <hal.feng@...rfivetech.com>,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH v3 01/11] dt-bindings: clock: Add StarFive JH7110
System-Top-Group clock and reset generator
On 14/03/2023 13:43, Xingyu Wu wrote:
> Add bindings for the System-Top-Group clock and reset generator (STGCRG)
> on the JH7110 RISC-V SoC by StarFive Ltd.
>
> Signed-off-by: Xingyu Wu <xingyu.wu@...rfivetech.com>
> ---
> .../clock/starfive,jh7110-stgcrg.yaml | 82 +++++++++++++++++++
> .../dt-bindings/clock/starfive,jh7110-crg.h | 34 ++++++++
> .../dt-bindings/reset/starfive,jh7110-crg.h | 28 +++++++
> 3 files changed, 144 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Best regards,
Krzysztof
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