[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20230315095437.187ac10c@gollum>
Date: Wed, 15 Mar 2023 09:54:37 +0100
From: Juerg Haefliger <juerg.haefliger@...onical.com>
To: Bjorn Andersson <quic_bjorande@...cinc.com>
Cc: Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Clark <robdclark@...il.com>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
Sean Paul <sean@...rly.run>,
Akhil P Oommen <quic_akhilpo@...cinc.com>,
Bjorn Andersson <andersson@...nel.org>,
<linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <dri-devel@...ts.freedesktop.org>,
<freedreno@...ts.freedesktop.org>, <johan@...nel.org>,
<mani@...nel.org>
Subject: Re: [PATCH 1/3] drm/msm/adreno: Add Adreno A690 support
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > index ca38b837dedb..437515e46e5a 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > @@ -355,6 +355,20 @@ static const struct adreno_info gpulist[] = {
> > .init = a6xx_gpu_init,
> > .zapfw = "a640_zap.mdt",
> > .hwcg = a640_hwcg,
> > + }, {
> > + .rev = ADRENO_REV(6, 9, 0, ANY_ID),
> > + .revn = 690,
> > + .name = "A690",
> > + .fw = {
> > + [ADRENO_FW_SQE] = "a660_sqe.fw",
> > + [ADRENO_FW_GMU] = "a690_gmu.bin",
> > + },
> > + .gmem = SZ_4M,
> > + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > + .init = a6xx_gpu_init,
> > + .zapfw = "a690_zap.mdt",
> > + .hwcg = a690_hwcg,
> > + .address_space_size = SZ_16G,
> > },
> > };
>
> This needs
>
> MODULE_FIRMWARE("qcom/a660_sqe.fw");
> MODULE_FIRMWARE("qcom/a690_gmu.bin");
> MODULE_FIRMWARE("qcom/a690_zap.mbn");
Eek. That should be
MODULE_FIRMWARE("qcom/a690_zap.mdt");
>
> ...Juerg
>
>
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > index b4f9b1343d63..da29bd392388 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > @@ -55,7 +55,7 @@ struct adreno_reglist {
> > u32 value;
> > };
> >
> > -extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
> > +extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[], a690_hwcg[];
> >
> > struct adreno_info {
> > struct adreno_rev rev;
> > @@ -272,6 +272,11 @@ static inline int adreno_is_a660(struct adreno_gpu *gpu)
> > return gpu->revn == 660;
> > }
> >
> > +static inline int adreno_is_a690(struct adreno_gpu *gpu)
> > +{
> > + return gpu->revn == 690;
> > +};
> > +
> > /* check for a615, a616, a618, a619 or any derivatives */
> > static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
> > {
> > @@ -286,7 +291,8 @@ static inline int adreno_is_a660_family(struct adreno_gpu *gpu)
> > /* check for a650, a660, or any derivatives */
> > static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
> > {
> > - return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu);
> > + return gpu->revn == 650 || gpu->revn == 620 || gpu->revn == 690 ||
> > + adreno_is_a660_family(gpu);
> > }
> >
> > u64 adreno_private_address_space_size(struct msm_gpu *gpu);
>
Content of type "application/pgp-signature" skipped
Powered by blists - more mailing lists