linux-kernel - Re: [PATCH v5 1/2] gpio: gpio-mlxbf3: Add gpio driver support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAHp75Vd5NhPcgUokJ0i8ftqVXjSB10q4VfxH9A7wcYhei-s2wA@mail.gmail.com>
Date:   Wed, 15 Mar 2023 11:15:38 +0200
From:   Andy Shevchenko <andy.shevchenko@...il.com>
To:     Asmaa Mnebhi <asmaa@...dia.com>
Cc:     linus.walleij@...aro.org, bgolaszewski@...libre.com,
        linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-acpi@...r.kernel.org
Subject: Re: [PATCH v5 1/2] gpio: gpio-mlxbf3: Add gpio driver support

On Wed, Mar 15, 2023 at 12:16 AM Asmaa Mnebhi <asmaa@...dia.com> wrote:
>
> Add support for the BlueField-3 SoC GPIO driver.
> This driver configures and handles GPIO interrupts. It also enables a user
> to manipulate certain GPIO pins via libgpiod tools or other kernel drivers.
> The usables pins are defined via the "gpio-reserved-ranges" property.

Thank you for the update, my comments below.

...

> +         This controller should be used in parallel with pinctrl-mlxbf to
> +         control the desired gpios.

GPIOs

Btw, have you considered renaming that driver to pinctrl-mlxbf3?

...

> +#include <linux/resource.h>

I dunno why you added this one.

The missing ones are:
err.h
io.h

...

> +       raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
> +       gpiochip_enable_irq(gc, offset);

No need to call this under the spin lock, or must be explained why.

> +       writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
> +
> +       val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
> +       val |= BIT(offset);
> +       writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
> +       raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);

...

> +       raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
> +       val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
> +       val &= ~BIT(offset);
> +       writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
> +       gpiochip_disable_irq(gc, offset);

Ditto.

> +       raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
> +}

...

> +/* This function needs to be defined for handle_edge_irq */

handle_edge_irq()

...

> +static const struct acpi_device_id __maybe_unused mlxbf3_gpio_acpi_match[] = {

Why __maybe_unused?

> +       { "MLNXBF33", 0 },
> +       {}
> +};

-- 
With Best Regards,
Andy Shevchenko