linux-kernel - [PATCH v3 1/5] dt-bindings: phy: Add StarFive JH7110 USB/PCIe document

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Date:   Wed, 15 Mar 2023 18:44:07 +0800
From:   Minda Chen <minda.chen@...rfivetech.com>
To:     Emil Renner Berthing <emil.renner.berthing@...onical.com>,
        Conor Dooley <conor@...nel.org>, Vinod Koul <vkoul@...nel.org>,
        Kishon Vijay Abraham I <kishon@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Pawel Laszczak <pawell@...ence.com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Peter Chen <peter.chen@...nel.org>,
        Roger Quadros <rogerq@...nel.org>,
        Philipp Zabel <p.zabel@...gutronix.de>
CC:     <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-phy@...ts.infradead.org>, <linux-usb@...r.kernel.org>,
        <linux-riscv@...ts.infradead.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        "Minda Chen" <minda.chen@...rfivetech.com>
Subject: [PATCH v3 1/5] dt-bindings: phy: Add StarFive JH7110 USB/PCIe document

Add StarFive JH7110 SoC USB 2.0/3.0 and PCIe 2.0 PHY dt-binding.
PCIe 2.0 phy can use as USB 3.0 PHY.

Signed-off-by: Minda Chen <minda.chen@...rfivetech.com>
---
 .../phy/starfive,jh7110-usb-pcie-phy.yaml     | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-pcie-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-pcie-phy.yaml
new file mode 100644
index 000000000000..aa1c3fe93100
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-pcie-phy.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive USB 2.0 and PCIe 2.0 PHY
+
+maintainers:
+  - Minda Chen <minda.chen@...rfivetech.com>
+
+properties:
+  compatible:
+    enum:
+      - starfive,jh7110-usb-phy
+      - starfive,jh7110-pcie-phy
+
+  reg:
+    maxItems: 1
+
+  "#phy-cells":
+    const: 0
+
+  clocks:
+    items:
+      - description: usb 125m clock
+      - description: app 125m clock
+
+  clock-names:
+    items:
+      - const: 125m
+      - const: app_125
+
+required:
+  - compatible
+  - reg
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    phy@...00000 {
+      compatible = "starfive,jh7110-usb-phy";
+      reg = <0x10200000 0x10000>;
+      clocks = <&syscrg 95>,
+               <&stgcrg 6>;
+      clock-names = "125m", "app_125";
+      #phy-cells = <0>;
+    };
+
+    phy@...10000 {
+      compatible = "starfive,jh7110-pcie-phy";
+      reg = <0x10210000 0x10000>;
+      #phy-cells = <0>;
+    };
+
+    phy@...20000 {
+      compatible = "starfive,jh7110-pcie-phy";
+      reg = <0x10220000 0x10000>;
+      #phy-cells = <0>;
+    };
-- 
2.17.1