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Message-ID: <SJ1PR11MB608394E7F78D116D09CAC26CFCBC9@SJ1PR11MB6083.namprd11.prod.outlook.com>
Date:   Thu, 16 Mar 2023 16:45:22 +0000
From:   "Luck, Tony" <tony.luck@...el.com>
To:     Shuai Xue <xueshuai@...ux.alibaba.com>,
        HORIGUCHI NAOYA(堀口 直也) 
        <naoya.horiguchi@....com>
CC:     "rafael@...nel.org" <rafael@...nel.org>,
        "lenb@...nel.org" <lenb@...nel.org>,
        "james.morse@....com" <james.morse@....com>,
        "bp@...en8.de" <bp@...en8.de>,
        "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
        "jarkko@...nel.org" <jarkko@...nel.org>,
        "linmiaohe@...wei.com" <linmiaohe@...wei.com>,
        "akpm@...ux-foundation.org" <akpm@...ux-foundation.org>,
        "xiexiuqi@...wei.com" <xiexiuqi@...wei.com>,
        "lvying6@...wei.com" <lvying6@...wei.com>,
        "linux-acpi@...r.kernel.org" <linux-acpi@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "cuibixuan@...ux.alibaba.com" <cuibixuan@...ux.alibaba.com>,
        "baolin.wang@...ux.alibaba.com" <baolin.wang@...ux.alibaba.com>,
        "zhuo.song@...ux.alibaba.com" <zhuo.song@...ux.alibaba.com>
Subject: RE: [PATCH v2 1/2] ACPI: APEI: set memory failure flags as
 MF_ACTION_REQUIRED on synchronous events

> On x86 platform with MCA, patrol scrub errors are asynchronous error, which are
> by default signaled with MCE. It is possible to downgrade the patrol scrub SRAO
> to UCNA or other correctable error in the logging/signaling behavior and signal
> CMCI only.
>
> As far as I know, on X86 platform, MCE is handled in do_machche_check() and only
> asynchronous error is notified through HEST. Can we safely drop ACPI_HEST_NOTIFY_MCE
> and only consider ACPI_HEST_NOTIFY_SEA as synchronous notification?
>
> Tony, do you have any comments on this? Please point out if I am wrong. Thank you.

You are correct. On x86 the HEST notifications are always asynchronous. The only
synchronous events are machine check with IA32_MCi_STATUS.AR == 1 (patrol
scrub and cache eviction machine checks are async and do not set this bit).

-Tony

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