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Message-ID: <e70030cb-e0b5-41ba-4913-361a2038e58a@intel.com>
Date: Thu, 16 Mar 2023 10:40:26 -0700
From: "Joseph, Jithu" <jithu.joseph@...el.com>
To: Hans de Goede <hdegoede@...hat.com>, <markgross@...nel.org>
CC: <tglx@...utronix.de>, <mingo@...hat.com>, <bp@...en8.de>,
<dave.hansen@...ux.intel.com>, <x86@...nel.org>, <hpa@...or.com>,
<gregkh@...uxfoundation.org>, <rostedt@...dmis.org>,
<ashok.raj@...el.com>, <tony.luck@...el.com>,
<linux-kernel@...r.kernel.org>,
<platform-driver-x86@...r.kernel.org>, <patches@...ts.linux.dev>,
<ravi.v.shankar@...el.com>, <thiago.macieira@...el.com>,
<athenas.jimenez.gonzalez@...el.com>, <sohil.mehta@...el.com>
Subject: Re: [PATCH v3 6/8] platform/x86/intel/ifs: Implement Array BIST test
On 3/16/2023 2:59 AM, Hans de Goede wrote:
>>
>> Only one IFS test is allowed at a time. This is done using "ifs_sem" defined in sysfs.c
>
> Ah I see.
>
> After taking a closer look I do see one unrelated issue with this patch
> sysfs.c: run_test_store() does:
>
> if (!ifsd->loaded)
> rc = -EPERM;
> else
> rc = do_core_test(cpu, dev);
>
> But AFAICT the loaded check really only applies to the first (intel_ifs_0 device) test type and the
> Array BIST test should work fine when loaded is false.
This is true, the load check only applies to first test. And the patch (5/8) in this series adds the
check you are suggesting to allow the second test to proceed (as given below)
if (ifsd->ro_info->test_num != IFS_TYPE_ARRAY_BIST && !ifsd->loaded)
rc = -EPERM;
else
rc = do_core_test(cpu, dev);
It is possible that the snippet you pasted above was from an earlier state.
Jithu
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