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Message-Id: <20230303-topic-sm6375_features0_dts-v2-9-708b8191f7eb@linaro.org>
Date: Thu, 16 Mar 2023 15:12:58 +0100
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Amit Kucheria <amitk@...nel.org>,
Thara Gopinath <thara.gopinath@...il.com>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Zhang Rui <rui.zhang@...el.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Georgi Djakov <djakov@...nel.org>,
Sibi Sankar <quic_sibis@...cinc.com>
Cc: linux-arm-msm@...r.kernel.org, linux-pm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Marijn Suijten <marijn.suijten@...ainline.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>
Subject: [PATCH v2 09/14] arm64: dts: qcom: sm6375: Add CPUCP L3 node
Configure the L3 cache DVFS scaler within the CPUCP block to allow
for dynamic frequency switching.
Reviewed-by: Sibi Sankar <quic_sibis@...cinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
---
arch/arm64/boot/dts/qcom/sm6375.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi
index 90f18754a63b..59d7ed25aa36 100644
--- a/arch/arm64/boot/dts/qcom/sm6375.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi
@@ -1505,6 +1505,15 @@ frame@...d000 {
};
};
+ cpucp_l3: interconnect@...0000 {
+ compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3";
+ reg = <0 0x0fd90000 0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@...1000 {
compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss";
reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>;
--
2.39.2
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