linux-kernel - Re: [PATCH 08/15] dt-bindings: clock: Document ma35d1 clock controller bindings

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Fri, 17 Mar 2023 17:52:37 +0800
From:   Jacky Huang <ychuang570808@...il.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        lee@...nel.org, mturquette@...libre.com, sboyd@...nel.org,
        p.zabel@...gutronix.de, gregkh@...uxfoundation.org,
        jirislaby@...nel.org
Cc:     devicetree@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org,
        schung@...oton.com, Jacky Huang <ychuang3@...oton.com>
Subject: Re: [PATCH 08/15] dt-bindings: clock: Document ma35d1 clock
 controller bindings

Dear Krzysztof,

Thanks for your advice.

On 2023/3/17 下午 05:13, Krzysztof Kozlowski wrote:
> On 17/03/2023 04:47, Jacky Huang wrote:
>>>> +
>>>> +  nuvoton,pll-mode:
>>>> +    description:
>>>> +      A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
>>>> +      EPLL, and VPLL in sequential. The operation mode value 0 is for
>>>> +      integer mode, 1 is for fractional mode, and 2 is for spread
>>>> +      spectrum mode.
>>>> +    $ref: /schemas/types.yaml#/definitions/uint32-array
>>>> +    maxItems: 5
>>>> +    items:
>>>> +      minimum: 0
>>>> +      maximum: 2
>>> Why exactly this is suitable for DT?
>> I will use strings instead.
> I have doubts why PLL mode is a property of DT. Is this a board-specific
> property?

CA-PLL has mode 0 only.
DDRPLL, APLL, EPLL, and VPLL have the same PLL design that supports
integer mode, fractional mode, and spread spctrum mode. The PLL mode
is controlled by clock controller register. I think it's not board-specific.

>>>> +
>>>> +  nuvoton,sys:
>>>> +    description:
>>>> +      Phandle to the system management controller.
>>>> +    $ref: "/schemas/types.yaml#/definitions/phandle-array"
>>> Drop quotes.
>>>
>>> You need here constraints, look for existing examples.
>>>
>> I would like to modify this as:
>>
>>
>>     nuvoton,sys:
>>       description:
>>         Use to unlock and lock some clock controller registers. The lock
>>         control register is in system controller.
>>       $ref: /schemas/types.yaml#/definitions/phandle-array
>>       items:
>>         - items:
>>             - description: phandle to the system controller.
> In such case you do not have array. Just make it phandle and drop the items.
>

Thank you.
So, I will rewrite it as

   nuvoton,sys:
     description:
       Use to unlock and lock some clock controller registers. The lock
       control register is in system controller.
     $ref: /schemas/types.yaml#/definitions/phandle


>
> Best regards,
> Krzysztof
>

Best regards,

Jacky Huang