linux-kernel - [PATCH 1/4] adjust init logic for ts-wxl to reflect single core dev

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Message-Id: <20230317154411.3727514-1-jeremy@jeremypeper.com>
Date:   Fri, 17 Mar 2023 10:43:44 -0500
From:   "Jeremy J. Peper" <jeremy@...emypeper.com>
To:     linux-kernel@...r.kernel.org, arnd@...nel.org
Cc:     "Jeremy J . Peper" <jeremy@...emypeper.com>,
        Andrew Lunn <andrew@...n.ch>,
        Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
        Gregory Clement <gregory.clement@...tlin.com>,
        Russell King <linux@...linux.org.uk>,
        linux-arm-kernel@...ts.infradead.org
Subject: [PATCH 1/4] adjust init logic for ts-wxl to reflect single core dev

Original code was largely copy-pasted from the reference board code, adjust pcie initialiazation to reflect the TS-WXL using the single-core variant of this SoC.
Correct pcie_port_size to be a power of 2 as required.

Signed-off-by: Jeremy J. Peper <jeremy@...emypeper.com>
---
 arch/arm/mach-mv78xx0/buffalo-wxl-setup.c | 12 ++----------
 arch/arm/mach-mv78xx0/pcie.c              |  2 +-
 2 files changed, 3 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
index 9aa765d4c..383dc6eab 100644
--- a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
+++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
@@ -125,16 +125,8 @@ static void __init wxl_init(void)
 
 static int __init wxl_pci_init(void)
 {
-	if (machine_is_terastation_wxl()) {
-		/*
-		 * Assign the x16 PCIe slot on the board to CPU core
-		 * #0, and let CPU core #1 have the four x1 slots.
-		 */
-		if (mv78xx0_core_index() == 0)
-			mv78xx0_pcie_init(0, 1);
-		else
-			mv78xx0_pcie_init(1, 0);
-	}
+	if (machine_is_terastation_wxl() && mv78xx0_core_index() == 0)
+                mv78xx0_pcie_init(1, 1);
 
 	return 0;
 }
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index 6190f538a..fa68b6394 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -42,7 +42,7 @@ void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
 
 u32 pcie_port_size[8] = {
 	0,
-	0x30000000,
+	0x20000000,
 	0x10000000,
 	0x10000000,
 	0x08000000,
-- 
2.30.2