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Message-Id: <ed327f8d-ac9f-454c-a005-0edb400be165@app.fastmail.com>
Date: Fri, 17 Mar 2023 16:52:04 +0100
From: "Arnd Bergmann" <arnd@...nel.org>
To: "Jeremy J. Peper" <jeremy@...emypeper.com>,
linux-kernel@...r.kernel.org
Cc: "Andrew Lunn" <andrew@...n.ch>,
"Sebastian Hesselbarth" <sebastian.hesselbarth@...il.com>,
"Gregory Clement" <gregory.clement@...tlin.com>,
"Russell King" <linux@...linux.org.uk>,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 1/4] adjust init logic for ts-wxl to reflect single core dev
On Fri, Mar 17, 2023, at 16:43, Jeremy J. Peper wrote:
> Original code was largely copy-pasted from the reference board code,
> adjust pcie initialiazation to reflect the TS-WXL using the single-core
> variant of this SoC.
> Correct pcie_port_size to be a power of 2 as required.
>
> Signed-off-by: Jeremy J. Peper <jeremy@...emypeper.com>
All four patches look good to me in this version,
Reviewed-by: Arnd Bergmann <arnd@...db.de>
Andrew/Sebastian/Gregory, please let me know if you have any comments
on this, and if you want to pick it up in the mvebu tree or I should
just apply them directly in the soc tree to save you the work.
If I apply them directly, I'd probably take patches 1, 2 and 4 as
bugfixes for 6.3, but leave patch 3 for the 6.4 merge window, unless
you have a different preference.
Arnd
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