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Message-ID: <87171ab8-9c6d-3978-6d34-4ae922361307@linaro.org> Date: Sun, 19 Mar 2023 12:06:13 +0100 From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org> To: Jacky Huang <ychuang570808@...il.com>, robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org, lee@...nel.org, mturquette@...libre.com, sboyd@...nel.org, p.zabel@...gutronix.de, gregkh@...uxfoundation.org, jirislaby@...nel.org Cc: devicetree@...r.kernel.org, linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org, schung@...oton.com, Jacky Huang <ychuang3@...oton.com> Subject: Re: [PATCH 11/15] arm64: dts: nuvoton: Add initial ma35d1 device tree On 18/03/2023 07:07, Jacky Huang wrote: > >> >>> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x13) | >>> + IRQ_TYPE_LEVEL_HIGH)>; >>> + }; >>> + >>> + uart0:serial@...00000 { >>> + compatible = "nuvoton,ma35d1-uart"; >>> + reg = <0x0 0x40700000 0x0 0x100>; >>> + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; >>> + clocks = <&clk UART0_GATE>; >>> + status = "okay"; >> Why? Drop the line... or convert it to disabled. Otherwise, why every >> SoC has serial0 enabled? Is it used internally? > > > uart0 is on all the way since this SoC booting from the MaskROM boot code, > > load arm-trusted-firmware, load bootloader, and finally load linux kernel. > > uart0 is also the Linux console. Are you sure? Maybe my board has UART0 disconnected. Best regards, Krzysztof
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