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Date:   Sun, 19 Mar 2023 17:07:03 +0100
From:   Frank Oltmanns <>
        Maxime Ripard <>,
        Chen-Yu Tsai <>, David Airlie <>,
        Daniel Vetter <>,
        Jernej Skrabec <>,
        Samuel Holland <>, (open list:DRM DRIVERS FOR ALLWINNER
        A10), (moderated list:ARM/Allwinner
        sunXi SoC support), (open list:ARM/Allwinner sunXi SoC support), (open list)
Cc:     Frank Oltmanns <>
Subject: [PATCH 0/1] Fixing the DSI dot clock on Allwinner

According to the Allwinner A64's BSP code, the PLL rate needs to be set to the following frequency when using DSI:
PLL rate = DCLK * bpp / lanes

Source: [1]
The relevant lines for DSI (ommisions and comments mine):
dclk_rate = lcdp->panel_info.lcd_dclk_freq * 1000000;
lcd_rate = dclk_rate * clk_info.dsi_div; // dsi_div = bpp/lane
pll_rate = lcd_rate * clk_info.lcd_div;  // lcd_div = 1 --> pll_rate = lcd_rate
dsi_rate = pll_rate / clk_info.dsi_div   // --> dsi_rate = dclk_rate
clk_set_rate(lcdp->clk_parent, pll_rate);

This was already discussed by Maxime, Jagan and Michael in the past in the thread following this message: [2]. Unfortunately, there never was a conclusion in the form of code.

The attached patch is a slight variation of a patch that is part of megi's kernel branch that many PinePhone distributions (e.g. postmarketOS) use [3]. It calculates the TCON clock rate by using the formula above and dividing it by SUN6I_DSI_TCON_DIV, in order to force the parent clock to be set to the correct rate.

If I read the thread following this message [2] correctly, this was also what Maxime had in mind.

Please also note that, unfortunately, I only have a single board and panel (namely the PinePhone) to test this on.



Frank Oltmanns (1):
  drm/sun4i: tcon: Fix setting PLL rate when using DSI

 drivers/gpu/drm/sun4i/sun4i_tcon.c | 46 ++++++++++++++++++++----------
 1 file changed, 31 insertions(+), 15 deletions(-)


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