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Message-ID: <d9c185a3-6176-7b37-c87a-498877f69c4a@starfivetech.com>
Date: Mon, 20 Mar 2023 10:41:04 +0800
From: Xingyu Wu <xingyu.wu@...rfivetech.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
CC: <linux-riscv@...ts.infradead.org>, <devicetree@...r.kernel.org>,
"Stephen Boyd" <sboyd@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Conor Dooley <conor@...nel.org>,
Emil Renner Berthing <kernel@...il.dk>,
Michael Turquette <mturquette@...libre.com>,
Rob Herring <robh+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Hal Feng <hal.feng@...rfivetech.com>,
William Qiu <william.qiu@...rfivetech.com>,
<linux-kernel@...r.kernel.org>, <linux-clk@...r.kernel.org>
Subject: Re: [PATCH v2 1/6] dt-bindings: clock: Add StarFive JH7110 PLL clock
generator
On 2023/3/19 20:25, Krzysztof Kozlowski wrote:
> On 16/03/2023 04:05, Xingyu Wu wrote:
>> Add bindings for the PLL clock generator on the JH7110 RISC-V SoC.
>>
>> Signed-off-by: Xingyu Wu <xingyu.wu@...rfivetech.com>
>
>
>> +
>> +examples:
>> + - |
>> + pllclk: pll-clock-controller {
>
> This should be just "clock-controller" (and drop the label).
Will modify to "clock-controller" and drop the label.
Thanks.
>
> With above
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
>
Best regards,
Xingyu Wu
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