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Message-ID: <ZBgm9QxXWJWpEuIl@matsya>
Date: Mon, 20 Mar 2023 14:57:17 +0530
From: Vinod Koul <vkoul@...nel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Cc: andersson@...nel.org, lpieralisi@...nel.org, robh@...nel.org,
kw@...ux.com, krzysztof.kozlowski+dt@...aro.org,
konrad.dybcio@...aro.org, bhelgaas@...gle.com, kishon@...nel.org,
linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH v3 12/13] phy: qcom-qmp-pcie: Add RC init sequence for
SDX55
On 08-03-23, 13:54, Manivannan Sadhasivam wrote:
> Add PCIe RC init sequence making use of the common init sequence. The RC
> mode additionally requires REFCLK_DRV_DSBL bit to set during powerup and
> powerdown.
Applied to phy/next, thanks
--
~Vinod
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