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Message-Id: <20230321190118.3327360-6-bhupesh.sharma@linaro.org>
Date: Wed, 22 Mar 2023 00:31:18 +0530
From: Bhupesh Sharma <bhupesh.sharma@...aro.org>
To: linux-arm-msm@...r.kernel.org
Cc: agross@...nel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, andersson@...nel.org,
bhupesh.sharma@...aro.org, bhupesh.linux@...il.com,
krzysztof.kozlowski@...aro.org, robh+dt@...nel.org,
konrad.dybcio@...aro.org, vladimir.zapolskiy@...aro.org,
rfoss@...nel.org
Subject: [PATCH 5/5] arm64: dts: qcom: sm8350: Add Crypto Engine support
Add crypto engine (CE) and CE BAM related nodes and definitions to
'sm8350.dtsi'.
Co-developed-by and Signed-off-by: Robert Foss <rfoss@...nel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@...aro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index b2f1ea4b671e..d017a0a11fcb 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1730,6 +1730,32 @@ ufs_mem_phy_lanes: phy@...7400 {
};
};
+ cryptobam: dma-controller@...4000 {
+ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+ reg = <0 0x01dc4000 0 0x24000>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ iommus = <&apps_smmu 0x584 0x0011>,
+ <&apps_smmu 0x586 0x0011>,
+ <&apps_smmu 0x594 0x0011>,
+ <&apps_smmu 0x596 0x0011>;
+ };
+
+ crypto: crypto@...a000 {
+ compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce";
+ reg = <0 0x01dfa000 0 0x6000>;
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x584 0x0011>,
+ <&apps_smmu 0x586 0x0011>,
+ <&apps_smmu 0x594 0x0011>,
+ <&apps_smmu 0x596 0x0011>;
+ interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
+ interconnect-names = "memory";
+ };
+
ipa: ipa@...0000 {
compatible = "qcom,sm8350-ipa";
--
2.38.1
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