Message-ID: <20230321193933.iccqqlg5mgegcsed@mobilestation>
Date:   Tue, 21 Mar 2023 22:39:33 +0300
From:   Serge Semin <fancer.lancer@...il.com>
To:     Cai Huoqing <cai.huoqing@...ux.dev>
Cc:     Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
        Vinod Koul <vkoul@...nel.org>,
        Jingoo Han <jingoohan1@...il.com>,
        Lorenzo Pieralisi <lpieralisi@...nel.org>,
        Krzysztof Wilczyński <kw@...ux.com>,
        Rob Herring <robh@...nel.org>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        linux-kernel@...r.kernel.org, dmaengine@...r.kernel.org,
        linux-pci@...r.kernel.org
Subject: Re: [PATCH v7 0/5] dmaengine: dw-edma: Add support for native HDMA

On Tue, Mar 21, 2023 at 08:21:33PM +0800, Cai Huoqing wrote:
> On 21 3月 23 11:34:07, Serge Semin wrote:
> > On Tue, Mar 21, 2023 at 10:31:47AM +0800, Cai Huoqing wrote:
> > > On 20 3月 23 15:14:01, Serge Semin wrote:
> > > > Hi Cai
> > > > 
> > > > On Wed, Mar 15, 2023 at 09:28:31AM +0800, Cai Huoqing wrote:
> > > > > Add support for HDMA NATIVE, as long the IP design has set
> > > > > the compatible register map parameter-HDMA_NATIVE,
> > > > > which allows compatibility for native HDMA register configuration.
> > > > > 
> > > > > The HDMA Hyper-DMA IP is an enhancement of the eDMA embedded-DMA IP.
> > > > > And the native HDMA registers are different from eDMA,
> > > > > so this patch add support for HDMA NATIVE mode.
> > > > > 
> > > > > HDMA write and read channels operate independently to maximize
> > > > > the performance of the HDMA read and write data transfer over
> > > > > the link When you configure the HDMA with multiple read channels,
> > > > > then it uses a round robin (RR) arbitration scheme to select
> > > > > the next read channel to be serviced.The same applies when
> > > > > youhave multiple write channels.
> > > > > 
> > > > > The native HDMA driver also supports a maximum of 16 independent
> > > > > channels (8 write + 8 read), which can run simultaneously.
> > > > > Both SAR (Source Address Register) and DAR (Destination Address Register)
> > > > > are aligned to byte.
> > > > 
> > > > It seems like we are getting towards the series finalization. I'll
> > > > test it out on my HW after v8 is submitted. Meanwhile could you please
> > > > clarify whether you have a real device with DW HDMA engine on board?
> > > 
> > 
> > > Our hardware is an AI Accelerartor(PCIE Card).
> > > 
> > > The device pci.ids is 1d22:3864
> > > in https://github.com/pciutils/pciids/blob/master/pci.ids
> > > line 24737,
> > > 
> > > "1d22  Baidu Technology
> > >         3684  Kunlun AI Accelerator
> > >         3685  Kunlun2 AI Accelerator [VF]"
> > > 
> > > And our device driver is not ready to upstream(will cost serveral
> > > 
> > > months to port DRM etc.),
> > 
> > Ok. Thanks for clarification. Could you please add me to the Cc-list of
> > the AI-accelerator patch when it's ready to be submitted for review. I am
> > not that familiar with the DRM-part, but would like to have a look at
> > the DMA-related code.

> Sure, I'll Cc you if I send the patches.

Great! Thanks in advance.

> 
> By the way, Why use native hdma:
> 
> Our device v1 also use dw-edma. But we find that navtive HDMA work better
> 
> in SRIOV on, channel CSR can be map to every VF instead of some global
> 
> regiter must in PF. So v2 use native hdma.

Good to know. Thanks.

-Serge(y)

> 
> Thanks,
> -Cai
> 
> > 
> > -Serge(y)
> > 
> > > 
> > > but I have taken this DW eDMA core into our driver test.
> > > 
> > > Thanks
> > > Cai-
> > > 
> > > > You keep submitting the DW eDMA driver core update, but there is no
> > > > glue-driver or low-level device driver patch for a real device which
> > > > would set the EDMA_MF_HDMA_NATIVE mapping.
> > > > 
> > > > -Serge(y)
> > > > 
> > > > > 
> > > > > Cai Huoqing (2):
> > > > >   dmaengine: dw-edma: Add support for native HDMA
> > > > >   dmaengine: dw-edma: Optimization in dw_edma_v0_core_handle_int
> > > > > 
> > > > > Cai huoqing (3):
> > > > >   dmaengine: dw-edma: Rename dw_edma_core_ops structure to
> > > > >     dw_edma_plat_ops
> > > > >   dmaengine: dw-edma: Create a new dw_edma_core_ops structure to
> > > > >     abstract controller operation
> > > > >   dmaengine: dw-edma: Add HDMA DebugFS support
> > > > > 
> > > > > v6->v7:
> > > > >   [1/5]
> > > > >   1.Update the commit log.
> > > > >   [2/5]
> > > > >   2.Revert dw_edma_core_handle_int back to dw-edma-core.h.
> > > > >   3.Fix code style.
> > > > >   [3/5]
> > > > >   4.Move the change of register file from patch[4/5] to patch[3/5].
> > > > >   5.Fix code style.
> > > > > 
> > > > > v6 link:
> > > > >   https://lore.kernel.org/lkml/20230310032342.17395-1-cai.huoqing@linux.dev/
> > > > > 
> > > > >  drivers/dma/dw-edma/Makefile                 |   8 +-
> > > > >  drivers/dma/dw-edma/dw-edma-core.c           |  86 ++----
> > > > >  drivers/dma/dw-edma/dw-edma-core.h           |  58 ++++
> > > > >  drivers/dma/dw-edma/dw-edma-pcie.c           |   4 +-
> > > > >  drivers/dma/dw-edma/dw-edma-v0-core.c        |  91 ++++--
> > > > >  drivers/dma/dw-edma/dw-edma-v0-core.h        |  14 +-
> > > > >  drivers/dma/dw-edma/dw-hdma-v0-core.c        | 277 +++++++++++++++++++
> > > > >  drivers/dma/dw-edma/dw-hdma-v0-core.h        |  17 ++
> > > > >  drivers/dma/dw-edma/dw-hdma-v0-debugfs.c     | 176 ++++++++++++
> > > > >  drivers/dma/dw-edma/dw-hdma-v0-debugfs.h     |  22 ++
> > > > >  drivers/dma/dw-edma/dw-hdma-v0-regs.h        | 130 +++++++++
> > > > >  drivers/pci/controller/dwc/pcie-designware.c |   2 +-
> > > > >  include/linux/dma/edma.h                     |   7 +-
> > > > >  13 files changed, 785 insertions(+), 107 deletions(-)
> > > > >  create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-core.c
> > > > >  create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-core.h
> > > > >  create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-debugfs.c
> > > > >  create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-debugfs.h
> > > > >  create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-regs.h
> > > > > 
> > > > > -- 
> > > > > 2.34.1
> > > > > 

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