linux-kernel - Re: [PATCH v5 0/2] Introduce ICSSG based ethernet Driver

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <CAH9NwWdiWtGsbyQRWCPros7iuSZTm_9fzJFPtuyiMoDg3TubuA@mail.gmail.com>
Date:   Tue, 21 Mar 2023 09:51:21 +0100
From:   Christian Gmeiner <christian.gmeiner@...il.com>
To:     MD Danish Anwar <danishanwar@...com>
Cc:     "Andrew F. Davis" <afd@...com>, Suman Anna <s-anna@...com>,
        Roger Quadros <rogerq@...nel.org>,
        YueHaibing <yuehaibing@...wei.com>,
        Vignesh Raghavendra <vigneshr@...com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Eric Dumazet <edumazet@...gle.com>,
        "David S. Miller" <davem@...emloft.net>, andrew@...n.ch, nm@...com,
        ssantosh@...nel.org, srk@...com, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, netdev@...r.kernel.org,
        linux-omap@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v5 0/2] Introduce ICSSG based ethernet Driver

Hi

Am Fr., 10. Feb. 2023 um 13:02 Uhr schrieb MD Danish Anwar <danishanwar@...com>:
>
> The Programmable Real-time Unit and Industrial Communication Subsystem
> Gigabit (PRU_ICSSG) is a low-latency microcontroller subsystem in the TI
> SoCs. This subsystem is provided for the use cases like the implementation
> of custom peripheral interfaces, offloading of tasks from the other
> processor cores of the SoC, etc.
>
> The subsystem includes many accelerators for data processing like
> multiplier and multiplier-accumulator. It also has peripherals like
> UART, MII/RGMII, MDIO, etc. Every ICSSG core includes two 32-bit
> load/store RISC CPU cores called PRUs.
>
> The above features allow it to be used for implementing custom firmware
> based peripherals like ethernet.
>
> This series adds the YAML documentation and the driver with basic EMAC
> support for TI AM654 Silicon Rev 2 SoC with the PRU_ICSSG Sub-system.
> running dual-EMAC firmware.
> This currently supports basic EMAC with 1Gbps and 100Mbps link. 10M and
> half-duplex modes are not yet supported because they require the support
> of an IEP, which will be added later.
> Advanced features like switch-dev and timestamping will be added later.

What are TI plans to support TI AM642 Silicon Rev 2?

-- 
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info/privacypolicy