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Message-Id: <20230323072714.82289-6-likexu@tencent.com>
Date: Thu, 23 Mar 2023 15:27:12 +0800
From: Like Xu <like.xu.linux@...il.com>
To: Sean Christopherson <seanjc@...gle.com>
Cc: Paolo Bonzini <pbonzini@...hat.com>,
Jinrong Liang <cloudliang@...cent.com>,
linux-kernel@...r.kernel.org, kvm@...r.kernel.org
Subject: [PATCH 5/7] KVM: selftests: Test Intel supported fixed counters bit mask
From: Like Xu <likexu@...cent.com>
Add a test to check that fixed counters enabled via guest
CPUID.0xA.ECX (instead of EDX[04:00]) work as normal as usual.
Signed-off-by: Like Xu <likexu@...cent.com>
---
.../selftests/kvm/x86_64/pmu_cpuid_test.c | 63 +++++++++++++++++++
1 file changed, 63 insertions(+)
diff --git a/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c b/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c
index c934144be287..79f2e144c6c6 100644
--- a/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c
+++ b/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c
@@ -199,6 +199,27 @@ static void intel_guest_run_arch_event(uint8_t version, uint8_t max_gp_num,
GUEST_DONE();
}
+static void intel_guest_run_fixed_counters(uint64_t supported_bitmask,
+ uint8_t max_fixed_num)
+{
+ unsigned int i;
+
+ for (i = 0; i < max_fixed_num; i++) {
+ if (!(supported_bitmask & BIT_ULL(i)))
+ continue;
+
+ wrmsr(MSR_CORE_PERF_FIXED_CTR0 + i, 0);
+ wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, BIT_ULL(4 * i));
+ wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, BIT_ULL(INTEL_PMC_IDX_FIXED + i));
+ __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES}));
+ wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
+
+ GUEST_SYNC(!!_rdpmc(RDPMC_FIXED_BASE | i));
+ }
+
+ GUEST_DONE();
+}
+
static void test_arch_events_setup(struct kvm_vcpu *vcpu, uint8_t evt_vector,
uint8_t unavl_mask, uint8_t idx)
{
@@ -279,6 +300,47 @@ static uint64_t test_oob_fixed_counter_setup(struct kvm_vcpu *vcpu,
return ret;
}
+static void test_fixed_counters_setup(struct kvm_vcpu *vcpu, uint8_t edx_fix_num,
+ uint32_t fixed_bitmask)
+{
+ struct kvm_cpuid_entry2 *entry;
+ uint8_t max_fixed_num = kvm_fixed_ctrs_num();
+ uint64_t supported_bitmask = 0;
+ unsigned int i;
+
+ entry = vcpu_get_cpuid_entry(vcpu, 0xa);
+ entry->ecx = fixed_bitmask;
+ entry->edx = (entry->edx & ~FIXED_CTR_NUM_MASK) | edx_fix_num;
+ vcpu_set_cpuid(vcpu);
+
+ for (i = 0; i < max_fixed_num; i++) {
+ if (entry->ecx & BIT_ULL(i) ||
+ ((entry->edx & FIXED_CTR_NUM_MASK) > i))
+ supported_bitmask |= BIT_ULL(i);
+ }
+
+ vcpu_args_set(vcpu, 2, supported_bitmask, max_fixed_num);
+ vm_install_exception_handler(vcpu->vm, GP_VECTOR, guest_gp_handler);
+}
+
+static void intel_test_fixed_counters(void)
+{
+ const char *msg = "At least one fixed counter is not working as expected";
+ uint8_t edx, num = kvm_fixed_ctrs_num();
+ struct kvm_vcpu *vcpu;
+ uint32_t ecx;
+
+ for (edx = 0; edx <= num; edx++) {
+ /* KVM doesn't emulate more fixed counters than it can support. */
+ for (ecx = 0; ecx <= (BIT_ULL(num) - 1); ecx++) {
+ vcpu = new_vcpu(intel_guest_run_fixed_counters);
+ test_fixed_counters_setup(vcpu, edx, ecx);
+ run_vcpu(vcpu, msg, first_uc_arg_equals, (void *)true);
+ free_vcpu(vcpu);
+ }
+ }
+}
+
static void intel_check_arch_event_is_unavl(uint8_t idx)
{
const char *msg = "Unavailable arch event is counting.";
@@ -383,6 +445,7 @@ static void intel_test_pmu_cpuid(void)
{
intel_test_arch_events();
intel_test_counters_num();
+ intel_test_fixed_counters();
}
int main(int argc, char *argv[])
--
2.40.0
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