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Date: Thu, 23 Mar 2023 10:08:21 +0100
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: airlied@...il.com
Cc: daniel@...ll.ch, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, wenst@...omium.org,
steven.price@....com, alyssa.rosenzweig@...labora.com,
robh@...nel.org, dri-devel@...ts.freedesktop.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
kernel@...labora.com,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
Subject: [PATCH v1 RESEND 1/2] dt-bindings: gpu: mali-bifrost: Document nvmem for speedbin support
Some SoCs implementing ARM Mali GPUs may be subject to speed binning
and the usable bin is read from nvmem: document the addition of nvmem
and nvmem-cells for 'speed-bin'.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
---
.../devicetree/bindings/gpu/arm,mali-bifrost.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
index 8a0083800810..1eecb014016c 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
@@ -104,6 +104,13 @@ properties:
dma-coherent: true
+ nvmem-cell-names:
+ items:
+ - const: speed-bin
+
+ nvmem-cells:
+ maxItems: 1
+
required:
- compatible
- reg
--
2.40.0
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