linux-kernel - Re: [PATCH v12 13/15] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Thu, 23 Mar 2023 12:42:02 +0200
From:   Andy Shevchenko <andy.shevchenko@...il.com>
To:     Brad Larson <blarson@....com>
Cc:     linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-mmc@...r.kernel.org, linux-spi@...r.kernel.org,
        adrian.hunter@...el.com, alcooperx@...il.com, arnd@...db.de,
        brendan.higgins@...ux.dev, briannorris@...omium.org,
        brijeshkumar.singh@....com, catalin.marinas@....com,
        davidgow@...gle.com, gsomlo@...il.com, gerg@...ux-m68k.org,
        krzk@...nel.org, krzysztof.kozlowski+dt@...aro.org, lee@...nel.org,
        lee.jones@...aro.org, broonie@...nel.org,
        yamada.masahiro@...ionext.com, p.zabel@...gutronix.de,
        piotrs@...ence.com, p.yadav@...com, rdunlap@...radead.org,
        robh+dt@...nel.org, samuel@...lland.org, fancer.lancer@...il.com,
        skhan@...uxfoundation.org, suravee.suthikulpanit@....com,
        thomas.lendacky@....com, tonyhuang.sunplus@...il.com,
        ulf.hansson@...aro.org, vaishnav.a@...com, will@...nel.org,
        devicetree@...r.kernel.org
Subject: Re: [PATCH v12 13/15] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support

On Thu, Mar 23, 2023 at 2:10 AM Brad Larson <blarson@....com> wrote:
>
> Add support for AMD Pensando Elba SoC which explicitly
> controls byte-lane enables on writes.
>
> Select MMC_SDHCI_IO_ACCESSORS for MMC_SDHCI_CADENCE which
> allows Elba SoC sdhci_elba_ops to overwrite the SDHCI
> IO memory accessors


> +/* Elba control register bits [6:3] are byte-lane enables */
> +#define ELBA_BYTE_ENABLE_MASK(x)       ((x) << 3)


> +static void elba_priv_writel(struct sdhci_cdns_priv *priv, u32 val,
> +                            void __iomem *reg)
> +{
> +       unsigned long flags;
> +
> +       spin_lock_irqsave(&priv->wrlock, flags);
> +       writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr);

GENMASK(3, 0) ?

> +       writel(val, reg);
> +       spin_unlock_irqrestore(&priv->wrlock, flags);
> +}

...

> +       byte_enables = GENMASK(1, 0) << (reg & 0x3);

   unsigned u32 shift = reg & GENMASK(1, 0);

   byte_enables = GENMASK(1, 0) << shift;

?

...

> +       byte_enables = BIT(0) << (reg & 0x3);

In a similar way?

   unsigned u32 shift = reg & GENMASK(1, 0);

   byte_enables = BIT(0) << shift;

-- 
With Best Regards,
Andy Shevchenko