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Message-Id: <20221209-dt-binding-ufs-v3-3-499dff23a03c@fairphone.com>
Date: Fri, 24 Mar 2023 08:41:30 +0100
From: Luca Weiss <luca.weiss@...rphone.com>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Alim Akhtar <alim.akhtar@...sung.com>,
Avri Altman <avri.altman@....com>,
Bart Van Assche <bvanassche@....org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Iskren Chernev <me@...ren.info>,
Manivannan Sadhasivam <mani@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, linux-scsi@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
~postmarketos/upstreaming@...ts.sr.ht, phone-devel@...r.kernel.org,
Luca Weiss <luca.weiss@...rphone.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: [PATCH v3 3/3] dt-bindings: ufs: qcom: Fix sm8450 bindings
SM8450 actually supports ICE (Inline Crypto Engine) so adjust the
bindings and the example to match.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Signed-off-by: Luca Weiss <luca.weiss@...rphone.com>
---
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index ebc8e1adbc6f..3af786120fa5 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -113,7 +113,6 @@ allOf:
- qcom,sc8280xp-ufshc
- qcom,sm8250-ufshc
- qcom,sm8350-ufshc
- - qcom,sm8450-ufshc
- qcom,sm8550-ufshc
then:
properties:
@@ -144,6 +143,7 @@ allOf:
- qcom,sdm845-ufshc
- qcom,sm6350-ufshc
- qcom,sm8150-ufshc
+ - qcom,sm8450-ufshc
then:
properties:
clocks:
@@ -250,7 +250,9 @@ examples:
ufs@...4000 {
compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
- reg = <0 0x01d84000 0 0x3000>;
+ reg = <0 0x01d84000 0 0x3000>,
+ <0 0x01d88000 0 0x8000>;
+ reg-names = "std", "ice";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
@@ -278,7 +280,8 @@ examples:
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
- "rx_lane1_sync_clk";
+ "rx_lane1_sync_clk",
+ "ice_core_clk";
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
@@ -286,7 +289,8 @@ examples:
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
- <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
+ <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
freq-table-hz = <75000000 300000000>,
<0 0>,
<0 0>,
@@ -294,6 +298,7 @@ examples:
<75000000 300000000>,
<0 0>,
<0 0>,
- <0 0>;
+ <0 0>,
+ <75000000 300000000>;
};
};
--
2.40.0
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