| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20230324143626.16336-4-clin@suse.com>
Date: Fri, 24 Mar 2023 22:36:24 +0800
From: Chester Lin <clin@...e.com>
To: Linus Walleij <linus.walleij@...aro.org>,
Andy Shevchenko <andy.shevchenko@...il.com>
Cc: Chester Lin <clin@...e.com>, NXP S32 Linux Team <s32@....com>,
linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Ghennadi Procopciuc <Ghennadi.Procopciuc@....nxp.com>,
Andrei Stefanescu <andrei.stefanescu@....com>,
Radu Pirea <radu-nicolae.pirea@....com>,
Andreas Färber <afaerber@...e.de>,
Matthias Brugger <mbrugger@...e.com>
Subject: [PATCH v4 3/5] pinctrl: s32cc: embed generic struct pingroup
Use generic data structure to describe pin control groups in S32 SoC family
and drop duplicated struct members.
Suggested-by: Andy Shevchenko <andy.shevchenko@...il.com>
Signed-off-by: Chester Lin <clin@...e.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@...il.com>
---
(No change since v3)
drivers/pinctrl/nxp/pinctrl-s32.h | 12 ++----
drivers/pinctrl/nxp/pinctrl-s32cc.c | 57 +++++++++++++++--------------
2 files changed, 33 insertions(+), 36 deletions(-)
diff --git a/drivers/pinctrl/nxp/pinctrl-s32.h b/drivers/pinctrl/nxp/pinctrl-s32.h
index 545bf16b988d..850cd668f406 100644
--- a/drivers/pinctrl/nxp/pinctrl-s32.h
+++ b/drivers/pinctrl/nxp/pinctrl-s32.h
@@ -15,16 +15,12 @@ struct platform_device;
/**
* struct s32_pin_group - describes an S32 pin group
- * @name: the name of this specific pin group
- * @npins: the number of pins in this group array, i.e. the number of
- * elements in pin_ids and pin_sss so we can iterate over that array
- * @pin_ids: an array of pin IDs in this group
- * @pin_sss: an array of source signal select configs paired with pin_ids
+ * @data: generic data describes group name, number of pins, and a pin array in
+ this group.
+ * @pin_sss: an array of source signal select configs paired with pin array.
*/
struct s32_pin_group {
- const char *name;
- unsigned int npins;
- unsigned int *pin_ids;
+ struct pingroup data;
unsigned int *pin_sss;
};
diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinctrl-s32cc.c
index 36f323f87785..e65c88162d7f 100644
--- a/drivers/pinctrl/nxp/pinctrl-s32cc.c
+++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c
@@ -188,7 +188,7 @@ static const char *s32_get_group_name(struct pinctrl_dev *pctldev,
struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct s32_pinctrl_soc_info *info = ipctl->info;
- return info->groups[selector].name;
+ return info->groups[selector].data.name;
}
static int s32_get_group_pins(struct pinctrl_dev *pctldev,
@@ -198,8 +198,8 @@ static int s32_get_group_pins(struct pinctrl_dev *pctldev,
struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct s32_pinctrl_soc_info *info = ipctl->info;
- *pins = info->groups[selector].pin_ids;
- *npins = info->groups[selector].npins;
+ *pins = info->groups[selector].data.pins;
+ *npins = info->groups[selector].data.npins;
return 0;
}
@@ -314,23 +314,23 @@ static int s32_pmx_set(struct pinctrl_dev *pctldev, unsigned int selector,
grp = &info->groups[group];
dev_dbg(ipctl->dev, "set mux for function %s group %s\n",
- info->functions[selector].name, grp->name);
+ info->functions[selector].name, grp->data.name);
/* Check beforehand so we don't have a partial config. */
- for (i = 0; i < grp->npins; i++) {
- if (s32_check_pin(pctldev, grp->pin_ids[i]) != 0) {
+ for (i = 0; i < grp->data.npins; i++) {
+ if (s32_check_pin(pctldev, grp->data.pins[i]) != 0) {
dev_err(info->dev, "invalid pin: %u in group: %u\n",
- grp->pin_ids[i], group);
+ grp->data.pins[i], group);
return -EINVAL;
}
}
- for (i = 0, ret = 0; i < grp->npins && !ret; i++) {
- ret = s32_regmap_update(pctldev, grp->pin_ids[i],
+ for (i = 0, ret = 0; i < grp->data.npins && !ret; i++) {
+ ret = s32_regmap_update(pctldev, grp->data.pins[i],
S32_MSCR_SSS_MASK, grp->pin_sss[i]);
if (ret) {
dev_err(info->dev, "Failed to set pin %u\n",
- grp->pin_ids[i]);
+ grp->data.pins[i]);
return ret;
}
}
@@ -606,8 +606,8 @@ static int s32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int selecto
int i, ret;
grp = &info->groups[selector];
- for (i = 0; i < grp->npins; i++) {
- ret = s32_pinconf_mscr_update(pctldev, grp->pin_ids[i],
+ for (i = 0; i < grp->data.npins; i++) {
+ ret = s32_pinconf_mscr_update(pctldev, grp->data.pins[i],
configs, num_configs);
if (ret)
return ret;
@@ -641,9 +641,9 @@ static void s32_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
seq_puts(s, "\n");
grp = &info->groups[selector];
- for (i = 0; i < grp->npins; i++) {
- name = pin_get_name(pctldev, grp->pin_ids[i]);
- ret = s32_regmap_read(pctldev, grp->pin_ids[i], &config);
+ for (i = 0; i < grp->data.npins; i++) {
+ name = pin_get_name(pctldev, grp->data.pins[i]);
+ ret = s32_regmap_read(pctldev, grp->data.pins[i], &config);
if (ret)
return;
seq_printf(s, "%s: 0x%x\n", name, config);
@@ -736,6 +736,7 @@ static int s32_pinctrl_parse_groups(struct device_node *np,
const __be32 *p;
struct device *dev;
struct property *prop;
+ unsigned int *pins, *sss;
int i, npins;
u32 pinmux;
@@ -744,38 +745,38 @@ static int s32_pinctrl_parse_groups(struct device_node *np,
dev_dbg(dev, "group: %pOFn\n", np);
/* Initialise group */
- grp->name = np->name;
+ grp->data.name = np->name;
npins = of_property_count_elems_of_size(np, "pinmux", sizeof(u32));
if (npins < 0) {
dev_err(dev, "Failed to read 'pinmux' property in node %s.\n",
- grp->name);
+ grp->data.name);
return -EINVAL;
}
if (!npins) {
- dev_err(dev, "The group %s has no pins.\n", grp->name);
+ dev_err(dev, "The group %s has no pins.\n", grp->data.name);
return -EINVAL;
}
- grp->npins = npins;
+ grp->data.npins = npins;
- grp->pin_ids = devm_kcalloc(info->dev, grp->npins,
- sizeof(unsigned int), GFP_KERNEL);
- grp->pin_sss = devm_kcalloc(info->dev, grp->npins,
- sizeof(unsigned int), GFP_KERNEL);
- if (!grp->pin_ids || !grp->pin_sss)
+ pins = devm_kcalloc(info->dev, npins, sizeof(*pins), GFP_KERNEL);
+ sss = devm_kcalloc(info->dev, npins, sizeof(*sss), GFP_KERNEL);
+ if (!pins || !sss)
return -ENOMEM;
i = 0;
of_property_for_each_u32(np, "pinmux", prop, p, pinmux) {
- grp->pin_ids[i] = get_pin_no(pinmux);
- grp->pin_sss[i] = get_pin_func(pinmux);
+ pins[i] = get_pin_no(pinmux);
+ sss[i] = get_pin_func(pinmux);
- dev_dbg(info->dev, "pin-id: 0x%x, sss: 0x%x",
- grp->pin_ids[i], grp->pin_sss[i]);
+ dev_dbg(info->dev, "pin: 0x%x, sss: 0x%x", pins[i], sss[i]);
i++;
}
+ grp->data.pins = pins;
+ grp->pin_sss = sss;
+
return 0;
}
--
2.37.3
Powered by blists - more mailing lists