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Message-ID: <10930783-e1dd-5e75-a2cc-a09af862d949@linaro.org>
Date:   Sun, 26 Mar 2023 11:37:16 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Shane Francis <bigbeeshane@...il.com>
Cc:     robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        heiko@...ech.de, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] dt-bindings: clock: update rk3588 clock definitions

On 26/03/2023 01:15, Shane Francis wrote:
> Some vendor uboot bootloaders use the target kernels
> DTB image to determine the target clock speeds for
> some PLLs, currently this can cause uboot to set the
> clock rate for gpll incorrectly on to cpll (breaking)

Please wrap commit message according to Linux coding style / submission
process (neither too early nor over the limit):
https://elixir.bootlin.com/linux/v5.18-rc4/source/Documentation/process/submitting-patches.rst#L586

> RGMII.
> 
> This change starts the PLL clock definitions from 1
> to correct this miss-match

Unfortunately the reason is not good enough for ABI break. Replace
vendor boot uboots with open-source one or just correct them (it's still
U-Boot so even for vendor one you have the source).

> 
> Signed-off-by: Shane Francis <bigbeeshane@...il.com>
> ---
>  .../dt-bindings/clock/rockchip,rk3588-cru.h   | 1442 ++++++++---------
>  1 file changed, 721 insertions(+), 721 deletions(-)
> 
> diff --git a/include/dt-bindings/clock/rockchip,rk3588-cru.h b/include/dt-bindings/clock/rockchip,rk3588-cru.h
> index b5616bca7b44..d63b07d054b7 100644
> --- a/include/dt-bindings/clock/rockchip,rk3588-cru.h
> +++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h
> @@ -12,727 +12,727 @@
>  
>  /* cru-clocks indices */
>  
> -#define PLL_B0PLL			0


Best regards,
Krzysztof

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