Date:   Mon, 27 Mar 2023 21:44:16 +0530
From:   Sumit Gupta <sumitg@...dia.com>
To:     <treding@...dia.com>, <krzysztof.kozlowski@...aro.org>,
        <dmitry.osipenko@...labora.com>, <viresh.kumar@...aro.org>,
        <rafael@...nel.org>, <jonathanh@...dia.com>, <robh+dt@...nel.org>,
        <lpieralisi@...nel.org>
CC:     <linux-kernel@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
        <linux-pm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-pci@...r.kernel.org>, <mmaddireddy@...dia.com>,
        <kw@...ux.com>, <bhelgaas@...gle.com>, <vidyas@...dia.com>,
        <sanjayc@...dia.com>, <ksitaraman@...dia.com>, <ishah@...dia.com>,
        <bbasu@...dia.com>, <sumitg@...dia.com>
Subject: [Patch v4 00/10] Tegra234 Memory interconnect support

Hi All,

Thank you for the review. Have incorporated the changes suggested in v3.
Requesting for ACK on the remaining patches if all fine.

The patches are divided into below groups:

- Patch [10]  : Memory Interconnect support in PCI (MC client)
  -- Need ACK.

- Patch [4-9]: Memory Interconnect support in CPUFREQ (MC client)
  -- 'Patch 5, 6 & 9' have ACK provided in v3 from Krzysztof.
  -- 'Patch 7 & 8' need ACK. 

- Patch [3-4]: Memory Interconnect base support
  -- 'Patch 4' has ACK provided in v3 from Krzysztof.
  -- 'Patch 3' removed ACK from Krzysztof as did suggested changes.

- Patch [1-2]: DT binding patch
  -- So, need ACK on 'Patch 1,2 & 3'.

Both the Memory Controller (MC) client patches are dependent on the 
'Patch [1-4]'.

Thank you,
Sumit Gupta
============

This patch series adds memory interconnect support for Tegra234 SoC.
It is used to dynamically scale DRAM Frequency as per the bandwidth
requests from different Memory Controller (MC) clients.
MC Clients use ICC Framework's icc_set_bw() api to dynamically request
for the DRAM bandwidth (BW). As per path, the request will be routed
from MC to the EMC driver. MC driver passes the request info like the
Client ID, type, and frequency request info to the BPMP-FW which will
set the final DRAM freq considering all exisiting requests.

MC and EMC are the ICC providers. Nodes in path for a request will be:
     Client[1-n] -> MC -> EMC -> EMEM/DRAM

The patch series also adds interconnect support in below clients:
1) CPUFREQ driver for scaling bandwidth with CPU frequency. For that,
   add per cluster OPP table which will be used in the CPUFREQ driver
   by requesting the minimum BW respective to the given CPU frequency
   in the OPP table of it's cluster.
2) PCIE driver to request BW required for different modes.

---
v3[3] -> v4:
- dropped 'patch 1' from v3 which returns 'struct tegra_bpmp *'.
- added 'patch 1 & 2' to get bpmp ref using 'nvidia,bpmp' property.
- dropped 'patch 10 & 11' from v3 and added those changes in 'patch 3'.
- added static to prototype of 'tegra_cpufreq_init_cpufreq_table()' to
  fix the warning reported by 'kernel test robot'.

v2[2] -> v3:
- in 'patch 7', set 'icc_dram_bw_scaling' to false if set_opp call failed
  to avoid flooding of uart with 'Failed to set bw' messages.
- added 'patch 10' to handle if the bpmp-fw is old and not support bwmgr mrq.
- added 'patch 11' to fix interconnect registration in tegra186-emc.
  ref patch link in linux next:
  [https://lore.kernel.org/all/20230306075651.2449-21-johan+linaro@kernel.org/]

v1[1] -> v2:
- moved BW setting to tegra234_mc_icc_set() from EMC driver.
- moved sw clients to the 'tegra_mc_clients' table.
- point 'node->data' to the entry within 'tegra_mc_clients'.
- removed 'struct tegra_icc_node' and get client info using 'node->data'.
- changed error handling in and around tegra_emc_interconnect_init().
- moved 'tegra-icc.h' from 'include/soc/tegra' to 'include/linux'.
- added interconnect support to PCIE driver in 'Patch 9'.
- merged 'Patch 9 & 10' from [1] to get num_channels and use.
- merged 'Patch 2 & 3' from [1] to add ISO and NISO clients.
- added 'Acked-by' of Krzysztof from 'Patch 05/10' of [1].
- Removed 'Patch 7' from [1] as that is merged now.

Sumit Gupta (10):
  dt-bindings: memory: tegra: add bpmp ref in tegra234-mc node
  arm64: tegra: add bpmp ref in tegra234-mc node
  memory: tegra: add interconnect support for DRAM scaling in Tegra234
  memory: tegra: add mc clients for Tegra234
  memory: tegra: add software mc clients in Tegra234
  dt-bindings: tegra: add icc ids for dummy MC clients
  arm64: tegra: Add cpu OPP tables and interconnects property
  cpufreq: tegra194: add OPP support and set bandwidth
  memory: tegra: make cpu cluster bw request a multiple of mc channels
  PCI: tegra194: add interconnect support in Tegra234

 .../nvidia,tegra186-mc.yaml                   |   7 +
 arch/arm64/boot/dts/nvidia/tegra234.dtsi      | 278 ++++++++
 drivers/cpufreq/tegra194-cpufreq.c            | 156 ++++-
 drivers/memory/tegra/mc.c                     |  24 +
 drivers/memory/tegra/mc.h                     |   1 +
 drivers/memory/tegra/tegra186-emc.c           | 125 ++++
 drivers/memory/tegra/tegra186.c               |   3 +
 drivers/memory/tegra/tegra234.c               | 600 +++++++++++++++++-
 drivers/pci/controller/dwc/pcie-tegra194.c    |  40 +-
 include/dt-bindings/memory/tegra234-mc.h      |   5 +
 include/linux/tegra-icc.h                     |  65 ++
 include/soc/tegra/mc.h                        |   8 +
 12 files changed, 1290 insertions(+), 22 deletions(-)
 create mode 100644 include/linux/tegra-icc.h

[1] https://lore.kernel.org/lkml/20221220160240.27494-1-sumitg@nvidia.com/T/
[2] https://lore.kernel.org/linux-tegra/20230220140559.28289-1-sumitg@nvidia.com/
[3] https://lore.kernel.org/lkml/20230320182441.11904-3-sumitg@nvidia.com/T/

-- 
2.17.1

Powered by blists - more mailing lists