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Message-Id: <20230327121317.4081816-9-arnd@kernel.org>
Date: Mon, 27 Mar 2023 14:13:04 +0200
From: Arnd Bergmann <arnd@...nel.org>
To: linux-kernel@...r.kernel.org
Cc: Arnd Bergmann <arnd@...db.de>, Vineet Gupta <vgupta@...nel.org>,
Russell King <linux@...linux.org.uk>,
Neil Armstrong <neil.armstrong@...aro.org>,
Linus Walleij <linus.walleij@...aro.org>,
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Subject: [PATCH 08/21] riscv: dma-mapping: only invalidate after DMA, not flush
From: Arnd Bergmann <arnd@...db.de>
No other architecture intentionally writes back dirty cache lines into
a buffer that a device has just finished writing into. If the cache is
clean, this has no effect at all, but if a cacheline in the buffer has
actually been written by the CPU, there is a drive bug that is likely
made worse by overwriting that buffer.
Signed-off-by: Arnd Bergmann <arnd@...db.de>
---
arch/riscv/mm/dma-noncoherent.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
index d919efab6eba..640f4c496d26 100644
--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -42,7 +42,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
break;
case DMA_FROM_DEVICE:
case DMA_BIDIRECTIONAL:
- ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
+ ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size);
break;
default:
break;
--
2.39.2
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