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Message-Id: <20230327121317.4081816-12-arnd@kernel.org>
Date: Mon, 27 Mar 2023 14:13:07 +0200
From: Arnd Bergmann <arnd@...nel.org>
To: linux-kernel@...r.kernel.org
Cc: Arnd Bergmann <arnd@...db.de>, Vineet Gupta <vgupta@...nel.org>,
Russell King <linux@...linux.org.uk>,
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Subject: [PATCH 11/21] mips: dma-mapping: skip invalidating before bidirectional DMA
From: Arnd Bergmann <arnd@...db.de>
Some architectures that need to invalidate buffers after bidirectional
DMA because of speculative prefetching only do a simpler writeback
before that DMA, while architectures that don't need to do the second
invalidate tend to have a combined writeback+invalidate before the
DMA.
The behavior on mips is slightly inconsistent, as it always
does the invalidation before bidirectional DMA and conditionally
does it a second time.
In order to make the behavior the same as the rest, change it
so that there is exactly one invalidation here, either before
or after the DMA.
Signed-off-by: Arnd Bergmann <arnd@...db.de>
---
arch/mips/mm/dma-noncoherent.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c
index 3c4fc97b9f39..b4350faf4f1e 100644
--- a/arch/mips/mm/dma-noncoherent.c
+++ b/arch/mips/mm/dma-noncoherent.c
@@ -65,7 +65,11 @@ static inline void dma_sync_virt_for_device(void *addr, size_t size,
dma_cache_inv((unsigned long)addr, size);
break;
case DMA_BIDIRECTIONAL:
- dma_cache_wback_inv((unsigned long)addr, size);
+ if (IS_ENABLED(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) &&
+ cpu_needs_post_dma_flush())
+ dma_cache_wback((unsigned long)addr, size);
+ else
+ dma_cache_wback_inv((unsigned long)addr, size);
break;
default:
BUG();
--
2.39.2
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