linux-kernel - Re: [PATCH v2 3/3] perf/amlogic: adjust register offsets

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Message-ID: <f0432ff5-7e73-1e7e-1745-6f3b679153fe@linaro.org>
Date:   Mon, 27 Mar 2023 16:17:29 +0200
From:   Neil Armstrong <neil.armstrong@...aro.org>
To:     Will Deacon <will@...nel.org>, Marc Gonzalez <mgonzalez@...ebox.fr>
Cc:     Marc Gonzalez <marc.w.gonzalez@...e.fr>,
        Jiucheng Xu <jiucheng.xu@...ogic.com>,
        Pierre-Hugues Husson <phh@....me>,
        Jerome Brunet <jbrunet@...libre.com>,
        Kevin Hilman <khilman@...libre.com>,
        linux-amlogic@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
        Mark Rutland <mark.rutland@....com>
Subject: Re: [PATCH v2 3/3] perf/amlogic: adjust register offsets

Hi,

On 27/03/2023 14:09, Marc Gonzalez wrote:
> Commit "perf/amlogic: resolve conflict between canvas & pmu"
> changed the base address.
> 
> Fixes: 2016e2113d35 ("perf/amlogic: Add support for Amlogic meson G12 SoC DDR PMU driver")
> Signed-off-by: Marc Gonzalez <mgonzalez@...ebox.fr>
> ---
>   drivers/perf/amlogic/meson_g12_ddr_pmu.c | 34 +++++++++++++++++-----------------
>   1 file changed, 17 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/perf/amlogic/meson_g12_ddr_pmu.c b/drivers/perf/amlogic/meson_g12_ddr_pmu.c
> index a78fdb15e26c2..8b643888d5036 100644
> --- a/drivers/perf/amlogic/meson_g12_ddr_pmu.c
> +++ b/drivers/perf/amlogic/meson_g12_ddr_pmu.c
> @@ -21,23 +21,23 @@
>   #define DMC_QOS_IRQ		BIT(30)
>   
>   /* DMC bandwidth monitor register address offset */
> -#define DMC_MON_G12_CTRL0		(0x20  << 2)
> -#define DMC_MON_G12_CTRL1		(0x21  << 2)
> -#define DMC_MON_G12_CTRL2		(0x22  << 2)
> -#define DMC_MON_G12_CTRL3		(0x23  << 2)
> -#define DMC_MON_G12_CTRL4		(0x24  << 2)
> -#define DMC_MON_G12_CTRL5		(0x25  << 2)
> -#define DMC_MON_G12_CTRL6		(0x26  << 2)
> -#define DMC_MON_G12_CTRL7		(0x27  << 2)
> -#define DMC_MON_G12_CTRL8		(0x28  << 2)
> -
> -#define DMC_MON_G12_ALL_REQ_CNT		(0x29  << 2)
> -#define DMC_MON_G12_ALL_GRANT_CNT	(0x2a  << 2)
> -#define DMC_MON_G12_ONE_GRANT_CNT	(0x2b  << 2)
> -#define DMC_MON_G12_SEC_GRANT_CNT	(0x2c  << 2)
> -#define DMC_MON_G12_THD_GRANT_CNT	(0x2d  << 2)
> -#define DMC_MON_G12_FOR_GRANT_CNT	(0x2e  << 2)
> -#define DMC_MON_G12_TIMER		(0x2f  << 2)
> +#define DMC_MON_G12_CTRL0		(0x0  << 2)
> +#define DMC_MON_G12_CTRL1		(0x1  << 2)
> +#define DMC_MON_G12_CTRL2		(0x2  << 2)
> +#define DMC_MON_G12_CTRL3		(0x3  << 2)
> +#define DMC_MON_G12_CTRL4		(0x4  << 2)
> +#define DMC_MON_G12_CTRL5		(0x5  << 2)
> +#define DMC_MON_G12_CTRL6		(0x6  << 2)
> +#define DMC_MON_G12_CTRL7		(0x7  << 2)
> +#define DMC_MON_G12_CTRL8		(0x8  << 2)
> +
> +#define DMC_MON_G12_ALL_REQ_CNT		(0x9  << 2)
> +#define DMC_MON_G12_ALL_GRANT_CNT	(0xa  << 2)
> +#define DMC_MON_G12_ONE_GRANT_CNT	(0xb  << 2)
> +#define DMC_MON_G12_SEC_GRANT_CNT	(0xc  << 2)
> +#define DMC_MON_G12_THD_GRANT_CNT	(0xd  << 2)
> +#define DMC_MON_G12_FOR_GRANT_CNT	(0xe  << 2)
> +#define DMC_MON_G12_TIMER		(0xf  << 2)
>   
>   /* Each bit represent a axi line */
>   PMU_FORMAT_ATTR(event, "config:0-7");


Reviewed-by: Neil Armstrong <neil.armstrong@...aro.org>

Will, I've applied DT patches 1 & 2, can you apply this one via your fixes tree for v6.3 ?

Thanks,
Neil