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Message-ID: <79968005-28f3-d890-dfea-faca2e7d7947@163.com> Date: Tue, 28 Mar 2023 10:29:04 +0800 From: Jiucheng Xu <jiuchengxu@....com> To: Will Deacon <will@...nel.org> Cc: Mark Rutland <mark.rutland@....com>, Neil Armstrong <neil.armstrong@...aro.org>, Kevin Hilman <khilman@...libre.com>, Jerome Brunet <jbrunet@...libre.com>, Martin Blumenstingl <martin.blumenstingl@...glemail.com>, Jianxin Pan <jianxin.pan@...ogic.com>, Kelvin Zhang <kelvin.zhang@...ogic.com>, Chris Healy <cphealy@...il.com>, Chris Healy <healych@...zon.com>, linux-amlogic@...ts.infradead.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org Subject: Re: [PATCH 2/3] perf/amlogic: Fix large number of counter issue My Amlogic email box has some issues. Use my personal email <jiucheng.xu@....com> to reply. On 2023/3/27 22:10, Will Deacon wrote: > [ EXTERNAL EMAIL ] > > On Thu, Feb 09, 2023 at 07:54:02PM +0800, Jiucheng Xu wrote: >> When use 1ms interval, very large number of counter happens >> once in a while as below: >> >> 25.968654513 281474976710655.84 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/ >> 26.118657346 281474976710655.88 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/ >> 26.180137180 281474976710655.66 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/ >> >> Root cause is the race between irq handler >> and pmu.read callback. Use spin lock to protect the sw&hw >> counters. >> >> Signed-off-by: Jiucheng Xu <jiucheng.xu@...ogic.com> >> --- >> drivers/perf/amlogic/meson_ddr_pmu_core.c | 10 +++++++++- >> 1 file changed, 9 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/perf/amlogic/meson_ddr_pmu_core.c b/drivers/perf/amlogic/meson_ddr_pmu_core.c >> index 0b24dee1ed3c..9b2e5d5c0626 100644 >> --- a/drivers/perf/amlogic/meson_ddr_pmu_core.c >> +++ b/drivers/perf/amlogic/meson_ddr_pmu_core.c >> @@ -14,6 +14,7 @@ >> #include <linux/perf_event.h> >> #include <linux/platform_device.h> >> #include <linux/printk.h> >> +#include <linux/spinlock.h> >> #include <linux/sysfs.h> >> #include <linux/types.h> >> >> @@ -23,6 +24,7 @@ struct ddr_pmu { >> struct pmu pmu; >> struct dmc_info info; >> struct dmc_counter counters; /* save counters from hw */ >> + spinlock_t lock; /* protect hw/sw counter */ >> bool pmu_enabled; >> struct device *dev; >> char *name; >> @@ -92,10 +94,12 @@ static void meson_ddr_perf_event_update(struct perf_event *event) >> int idx; >> int chann_nr = pmu->info.hw_info->chann_nr; >> >> + spin_lock(&pmu->lock); > Why doesn't this need the _irqsave() variant if we're racing with the irq > handler? > > Will I think meson_ddr_perf_event_update function is called with hard irq off. So update function couldn't be interrupted by irq handler. Right? Thanks, Jiucheng >
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