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Message-ID: <a2aae3a9-1d72-0b35-68cf-8fa3d28517c9@starfivetech.com>
Date:   Tue, 28 Mar 2023 09:42:02 +0800
From:   Hal Feng <hal.feng@...rfivetech.com>
To:     Conor Dooley <conor@...nel.org>
CC:     <linux-clk@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-riscv@...ts.infradead.org>, Stephen Boyd <sboyd@...nel.org>,
        "Michael Turquette" <mturquette@...libre.com>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Ben Dooks <ben.dooks@...ive.com>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>,
        "Emil Renner Berthing" <emil.renner.berthing@...onical.com>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v6 00/21] Basic clock, reset & device tree support for
 StarFive JH7110 RISC-V SoC

On Mon, 27 Mar 2023 23:50:18 +0100, Conor Dooley wrote:
> Hey Hal,
> 
> On Mon, Mar 20, 2023 at 06:37:29PM +0800, Hal Feng wrote:
>> This patch series adds basic clock, reset & DT support for StarFive
>> JH7110 SoC.
> 
> Probably obvious at this point given the number of outstanding comments
> on this version, but I'm gonna mark this series as "Changes Requested"
> on the RISC-V patchwork. I'm not sure what Stephen's cutoff for stuff is,
> but I'd like to have stuff ready to go to Arnd for -rc6, so you still
> have some time for another revision I think :)

Thanks for reminding. I will submit the next revision today or tomorrow.

Best regards,
Hal

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