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Message-ID: <30a9f919-ff6b-57cf-de34-e145a4474643@foss.st.com>
Date: Tue, 28 Mar 2023 11:39:19 +0200
From: Alexandre TORGUE <alexandre.torgue@...s.st.com>
To: <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<linux@...pel-privat.de>
CC: <linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] ARM: dts: stm32: fix spi1 pin assignment on stm32mp15
On 3/20/23 18:11, Alexandre Torgue wrote:
> Bank A and B IOs can't be handled by the pin controller 'Z'. This patch
> assign spi1 pin definition to the correct controller.
>
> Fixes: 9ad65d245b7b ("ARM: dts: stm32: stm32mp15-pinctrl: add spi1-1 pinmux group")
>
> Signed-off-by: Alexandre Torgue <alexandre.torgue@...s.st.com>
>
> diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
> index a9d2bec99014..e15a3b2a9b39 100644
> --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
> @@ -1880,6 +1880,21 @@
> };
> };
>
> + spi1_pins_b: spi1-1 {
> + pins1 {
> + pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
> + <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <1>;
> + };
> +
> + pins2 {
> + pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
> + bias-disable;
> + };
> + };
> +
> spi2_pins_a: spi2-0 {
> pins1 {
> pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
> @@ -2448,19 +2463,4 @@
> bias-disable;
> };
> };
> -
> - spi1_pins_b: spi1-1 {
> - pins1 {
> - pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
> - <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
> - bias-disable;
> - drive-push-pull;
> - slew-rate = <1>;
> - };
> -
> - pins2 {
> - pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
> - bias-disable;
> - };
> - };
> };
Applied on stm32-next.
Thanks.
Alex
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