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Message-Id: <20230328-topic-msgram_mpm-v1-1-1b788a5f5a33@linaro.org>
Date: Tue, 28 Mar 2023 12:02:52 +0200
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Shawn Guo <shawn.guo@...aro.org>
Cc: Marijn Suijten <marijn.suijten@...ainline.org>,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org,
Konrad Dybcio <konrad.dybcio@...aro.org>
Subject: [PATCH 1/2] dt-bindings: interrupt-controller: mpm: Allow passing
reg through phandle
Due to the wild nature of the Qualcomm RPM Message RAM, we can't really
use 'reg' to point to the MPM's slice of Message RAM without cutting into
an already-defined RPM MSG RAM node used for GLINK and SMEM.
Document passing the register space as a slice of SRAM through the
qcom,rpm-msg-ram property. This also makes 'reg' no longer required.
Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
---
.../devicetree/bindings/interrupt-controller/qcom,mpm.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml
index 509d20c091af..77fe5e0b378f 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml
@@ -30,6 +30,11 @@ properties:
description:
Specifies the base address and size of vMPM registers in RPM MSG RAM.
+ qcom,rpm-msg-ram:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the APSS MPM slice of the RPM Message RAM
+
interrupts:
maxItems: 1
description:
@@ -64,7 +69,6 @@ properties:
required:
- compatible
- - reg
- interrupts
- mboxes
- interrupt-controller
--
2.40.0
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