| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <CAA8EJprgcMOX-WRXP2i9k850La1A1UKaKuODd-fVi27nOxMbyA@mail.gmail.com>
Date: Tue, 28 Mar 2023 13:39:05 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Devi Priya <quic_devipriy@...cinc.com>
Cc: agross@...nel.org, andersson@...nel.org, konrad.dybcio@...aro.org,
robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
mturquette@...libre.com, sboyd@...nel.org,
linus.walleij@...aro.org, catalin.marinas@....com, will@...nel.org,
p.zabel@...gutronix.de, shawnguo@...nel.org, arnd@...db.de,
marcel.ziswiler@...adex.com, nfraprado@...labora.com,
broonie@...nel.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, linux-gpio@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, quic_srichara@...cinc.com,
quic_gokulsri@...cinc.com, quic_sjaganat@...cinc.com,
quic_kathirav@...cinc.com, quic_arajkuma@...cinc.com,
quic_anusha@...cinc.com, quic_poovendh@...cinc.com
Subject: Re: [PATCH V10 3/4] arm64: dts: qcom: Add support for ipq9574 SoC and
RDP433 variant
On Tue, 28 Mar 2023 at 10:31, Devi Priya <quic_devipriy@...cinc.com> wrote:
> On 3/27/2023 8:15 PM, Dmitry Baryshkov wrote:
> > On Mon, 27 Mar 2023 at 16:28, Devi Priya <quic_devipriy@...cinc.com> wrote:
> >>
> >> Add initial device tree support for Qualcomm IPQ9574 SoC and
> >> Reference Design Platform(RDP) 433 which is based on IPQ9574
> >> family of SoCs
> >>
> >> Co-developed-by: Anusha Rao <quic_anusha@...cinc.com>
> >> Signed-off-by: Anusha Rao <quic_anusha@...cinc.com>
> >> Co-developed-by: Poovendhan Selvaraj <quic_poovendh@...cinc.com>
> >> Signed-off-by: Poovendhan Selvaraj <quic_poovendh@...cinc.com>
> >> Signed-off-by: Devi Priya <quic_devipriy@...cinc.com>
> >> ---
> >> Changes in V10:
> >> - Renamed the Board Device Tree Source to use the RDP numbers
> >> - Updated the Makefile, subject and commit message accordingly
> >>
> >> arch/arm64/boot/dts/qcom/Makefile | 1 +
> >> arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 84 ++++++
> >> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 270 ++++++++++++++++++++
> >> 3 files changed, 355 insertions(+)
> >> create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> >> create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> >> index 1a29403400b7..52f1f92c5195 100644
> >> --- a/arch/arm64/boot/dts/qcom/Makefile
> >> +++ b/arch/arm64/boot/dts/qcom/Makefile
> >> @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
> >> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
> >> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
> >> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb
> >> +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb
> >> dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb
> >> dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
> >> dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb
> >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> >> new file mode 100644
> >> index 000000000000..2ce8e09e7565
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> >> @@ -0,0 +1,84 @@
> >> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> >> +/*
> >> + * IPQ9574 RDP433 board device tree source
> >> + *
> >> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
> >> + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
> >> + */
> >> +
> >> +/dts-v1/;
> >> +
> >> +#include "ipq9574.dtsi"
> >> +
> >> +/ {
> >> + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
> >> + compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
> >> +
> >> + aliases {
> >> + serial0 = &blsp1_uart2;
> >> + };
> >> +
> >> + chosen {
> >> + stdout-path = "serial0:115200n8";
> >> + };
> >> +};
> >> +
> >> +&blsp1_uart2 {
> >> + pinctrl-0 = <&uart2_pins>;
> >> + pinctrl-names = "default";
> >> + status = "okay";
> >> +};
> >> +
> >> +&sdhc_1 {
> >> + pinctrl-0 = <&sdc_default_state>;
> >> + pinctrl-names = "default";
> >> + mmc-ddr-1_8v;
> >> + mmc-hs200-1_8v;
> >> + mmc-hs400-1_8v;
> >> + mmc-hs400-enhanced-strobe;
> >> + max-frequency = <384000000>;
> >> + bus-width = <8>;
> >> + status = "okay";
> >> +};
> >> +
> >> +&sleep_clk {
> >> + clock-frequency = <32000>;
> >> +};
> >> +
> >> +&tlmm {
> >> + sdc_default_state: sdc-default-state {
> >> + clk-pins {
> >> + pins = "gpio5";
> >> + function = "sdc_clk";
> >> + drive-strength = <8>;
> >> + bias-disable;
> >> + };
> >> +
> >> + cmd-pins {
> >> + pins = "gpio4";
> >> + function = "sdc_cmd";
> >> + drive-strength = <8>;
> >> + bias-pull-up;
> >> + };
> >> +
> >> + data-pins {
> >> + pins = "gpio0", "gpio1", "gpio2",
> >> + "gpio3", "gpio6", "gpio7",
> >> + "gpio8", "gpio9";
> >> + function = "sdc_data";
> >> + drive-strength = <8>;
> >> + bias-pull-up;
> >> + };
> >> +
> >> + rclk-pins {
> >> + pins = "gpio10";
> >> + function = "sdc_rclk";
> >> + drive-strength = <8>;
> >> + bias-pull-down;
> >> + };
> >> + };
> >> +};
> >> +
> >> +&xo_board_clk {
> >> + clock-frequency = <24000000>;
> >> +};
> >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> >> new file mode 100644
> >> index 000000000000..3bb7435f5e7f
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> >> @@ -0,0 +1,270 @@
> >> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> >> +/*
> >> + * IPQ9574 SoC device tree source
> >> + *
> >> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
> >> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> >> + */
> >> +
> >> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> >> +#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
> >> +#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
> >> +
> >> +/ {
> >> + interrupt-parent = <&intc>;
> >> + #address-cells = <2>;
> >> + #size-cells = <2>;
> >> +
> >> + clocks {
> >> + bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk {
> >> + compatible = "fixed-clock";
> >> + clock-frequency = <353000000>;
> >> + #clock-cells = <0>;
> >> + };
> >
> > What is the source for this clock? With it clocking at 353 MHz, I
> > doubt that it is an external clock.
> bias_pll_ubi_nc_clk (353MHz)is a backup source
> for Q6_AXIM2_CLK/PCIE2_AXIM_CLK/PCIE3_AXIM_CLK/SNOC-CLK
> It is from the CMN_PLL, and is the same as that of PPE core clock.
> Do you suggest to move its clock-frequency to Board DT similar to
> xo/sleep clock?
No, I suggest moving it to the device where it originates. If it comes
from GCC, it should be provided by the GCC, not by the top-level fixed
clock.
> >
> >> +
> >> + sleep_clk: sleep-clk {
> >> + compatible = "fixed-clock";
> >> + #clock-cells = <0>;
> >> + };
> >> +
> >> + xo_board_clk: xo-board-clk {
> >> + compatible = "fixed-clock";
> >> + #clock-cells = <0>;
> >> + };
> >> + };
> >
> > [skipped the rest]
> >
> Regards,
> Devi Priya
--
With best wishes
Dmitry
Powered by blists - more mailing lists