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Message-Id: <837F1B2F-7090-4F9F-A894-594ACF6A8DB2@jrtc27.com>
Date: Wed, 29 Mar 2023 22:51:54 +0100
From: Jessica Clarke <jrtc27@...c27.com>
To: Arnd Bergmann <arnd@...nel.org>
Cc: Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
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Subject: Re: [PATCH 08/21] riscv: dma-mapping: only invalidate after DMA, not
flush
On 27 Mar 2023, at 13:13, Arnd Bergmann <arnd@...nel.org> wrote:
>
> From: Arnd Bergmann <arnd@...db.de>
>
> No other architecture intentionally writes back dirty cache lines into
> a buffer that a device has just finished writing into. If the cache is
> clean, this has no effect at all, but if a cacheline in the buffer has
> actually been written by the CPU, there is a drive bug that is likely
> made worse by overwriting that buffer.
FYI [1] proposed this same change a while ago but its justification was
flawed (which was my objection at the time, not the diff itself).
Jess
[1] https://lore.kernel.org/all/20220818165105.99746-1-s.miroshnichenko@yadro.com
> Signed-off-by: Arnd Bergmann <arnd@...db.de>
> ---
> arch/riscv/mm/dma-noncoherent.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
> index d919efab6eba..640f4c496d26 100644
> --- a/arch/riscv/mm/dma-noncoherent.c
> +++ b/arch/riscv/mm/dma-noncoherent.c
> @@ -42,7 +42,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
> break;
> case DMA_FROM_DEVICE:
> case DMA_BIDIRECTIONAL:
> - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
> + ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size);
> break;
> default:
> break;
> --
> 2.39.2
>
>
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> http://lists.infradead.org/mailman/listinfo/linux-riscv
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