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Message-ID: <CAFGrd9qS4mzXWRftbR7dFqtvs9Uc4qzBQMAjRo3rAwN70jDoyA@mail.gmail.com>
Date: Thu, 30 Mar 2023 01:17:01 +0200
From: Alexandre Mergnat <amergnat@...libre.com>
To: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
Cc: matthias.bgg@...il.com, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, flora.fu@...iatek.com,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, kernel@...labora.com,
phone-devel@...r.kernel.org, ~postmarketos/upstreaming@...ts.sr.ht
Subject: Re: [PATCH v2 5/6] soc: mediatek: mtk-pmic-wrap: Add support for
MT6331 w/ MT6332 companion
Reviewed-by: Alexandre Mergnat <amergnat@...libre.com>
Regards,
Alexandre
Le ven. 24 mars 2023 à 10:42, AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com> a écrit :
>
> Add support for the MT6331 PMIC and for its companion MT6332 PMIC.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
> ---
> drivers/soc/mediatek/mtk-pmic-wrap.c | 47 ++++++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
> index 366e40b802e4..ceeac43f7bd1 100644
> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
> @@ -170,6 +170,40 @@ static const u32 mt6323_regs[] = {
> [PWRAP_DEW_RDDMY_NO] = 0x01a4,
> };
>
> +static const u32 mt6331_regs[] = {
> + [PWRAP_DEW_DIO_EN] = 0x018c,
> + [PWRAP_DEW_READ_TEST] = 0x018e,
> + [PWRAP_DEW_WRITE_TEST] = 0x0190,
> + [PWRAP_DEW_CRC_SWRST] = 0x0192,
> + [PWRAP_DEW_CRC_EN] = 0x0194,
> + [PWRAP_DEW_CRC_VAL] = 0x0196,
> + [PWRAP_DEW_MON_GRP_SEL] = 0x0198,
> + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x019a,
> + [PWRAP_DEW_CIPHER_IV_SEL] = 0x019c,
> + [PWRAP_DEW_CIPHER_EN] = 0x019e,
> + [PWRAP_DEW_CIPHER_RDY] = 0x01a0,
> + [PWRAP_DEW_CIPHER_MODE] = 0x01a2,
> + [PWRAP_DEW_CIPHER_SWRST] = 0x01a4,
> + [PWRAP_DEW_RDDMY_NO] = 0x01a6,
> +};
> +
> +static const u32 mt6332_regs[] = {
> + [PWRAP_DEW_DIO_EN] = 0x80f6,
> + [PWRAP_DEW_READ_TEST] = 0x80f8,
> + [PWRAP_DEW_WRITE_TEST] = 0x80fa,
> + [PWRAP_DEW_CRC_SWRST] = 0x80fc,
> + [PWRAP_DEW_CRC_EN] = 0x80fe,
> + [PWRAP_DEW_CRC_VAL] = 0x8100,
> + [PWRAP_DEW_MON_GRP_SEL] = 0x8102,
> + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x8104,
> + [PWRAP_DEW_CIPHER_IV_SEL] = 0x8106,
> + [PWRAP_DEW_CIPHER_EN] = 0x8108,
> + [PWRAP_DEW_CIPHER_RDY] = 0x810a,
> + [PWRAP_DEW_CIPHER_MODE] = 0x810c,
> + [PWRAP_DEW_CIPHER_SWRST] = 0x810e,
> + [PWRAP_DEW_RDDMY_NO] = 0x8110,
> +};
> +
> static const u32 mt6351_regs[] = {
> [PWRAP_DEW_DIO_EN] = 0x02F2,
> [PWRAP_DEW_READ_TEST] = 0x02F4,
> @@ -1182,6 +1216,8 @@ static int mt8186_regs[] = {
>
> enum pmic_type {
> PMIC_MT6323,
> + PMIC_MT6331,
> + PMIC_MT6332,
> PMIC_MT6351,
> PMIC_MT6357,
> PMIC_MT6358,
> @@ -2041,6 +2077,16 @@ static const struct pwrap_slv_type pmic_mt6323 = {
> PWRAP_SLV_CAP_SECURITY,
> };
>
> +static const struct pwrap_slv_type pmic_mt6331 = {
> + .dew_regs = mt6331_regs,
> + .type = PMIC_MT6331,
> + .comp_dew_regs = mt6332_regs,
> + .comp_type = PMIC_MT6332,
> + .regops = &pwrap_regops16,
> + .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
> + PWRAP_SLV_CAP_SECURITY,
> +};
> +
> static const struct pwrap_slv_type pmic_mt6351 = {
> .dew_regs = mt6351_regs,
> .type = PMIC_MT6351,
> @@ -2086,6 +2132,7 @@ static const struct pwrap_slv_type pmic_mt6397 = {
>
> static const struct of_device_id of_slave_match_tbl[] = {
> { .compatible = "mediatek,mt6323", .data = &pmic_mt6323 },
> + { .compatible = "mediatek,mt6331", .data = &pmic_mt6331 },
> { .compatible = "mediatek,mt6351", .data = &pmic_mt6351 },
> { .compatible = "mediatek,mt6357", .data = &pmic_mt6357 },
> { .compatible = "mediatek,mt6358", .data = &pmic_mt6358 },
> --
> 2.40.0
>
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