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Message-ID: <36f75c71-cf5b-7cbd-8eac-8a8f628d1201@linaro.org>
Date:   Wed, 29 Mar 2023 10:21:41 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Jacky Huang <ychuang570808@...il.com>, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, lee@...nel.org,
        mturquette@...libre.com, sboyd@...nel.org, p.zabel@...gutronix.de,
        gregkh@...uxfoundation.org, jirislaby@...nel.org
Cc:     devicetree@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org,
        arnd@...db.de, schung@...oton.com, mjchen@...oton.com,
        Jacky Huang <ychuang3@...oton.com>
Subject: Re: [PATCH v6 08/12] arm64: dts: nuvoton: Add initial ma35d1 device
 tree

On 28/03/2023 04:19, Jacky Huang wrote:
> From: Jacky Huang <ychuang3@...oton.com>
> 
> Add initial device tree support for Nuvoton ma35d1 SoC, including
> cpu, clock, reset, and serial controllers.
> Add reference boards som-256m and iot-512m.
> 
> Signed-off-by: Jacky Huang <ychuang3@...oton.com>



> +	gic: interrupt-controller@...01000 {
> +		compatible = "arm,gic-400";
> +		reg =   <0x0 0x50801000 0 0x1000>, /* GICD */
> +			<0x0 0x50802000 0 0x2000>, /* GICC */
> +			<0x0 0x50804000 0 0x2000>, /* GICH */
> +			<0x0 0x50806000 0 0x2000>; /* GICV */
> +		#interrupt-cells = <3>;
> +		interrupt-parent = <&gic>;
> +		interrupt-controller;
> +		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x13) |
> +			      IRQ_TYPE_LEVEL_HIGH)>;
> +	};
> +
> +	uart0:serial@...00000 {

There is always space after label:.


Best regards,
Krzysztof

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