[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <c575ac46-28bf-254f-a3c1-e30885ba7933@gmail.com>
Date: Thu, 30 Mar 2023 19:28:53 +0200
From: Matthias Brugger <matthias.bgg@...il.com>
To: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
Alexandre Mergnat <amergnat@...libre.com>,
Wim Van Sebroeck <wim@...ux-watchdog.org>,
Guenter Roeck <linux@...ck-us.net>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Chaotian Jing <chaotian.jing@...iatek.com>,
Ulf Hansson <ulf.hansson@...aro.org>,
Wenbin Mei <wenbin.mei@...iatek.com>,
Linus Walleij <linus.walleij@...aro.org>,
Zhiyong Tao <zhiyong.tao@...iatek.com>,
Bernhard Rosenkränzer <bero@...libre.com>
Cc: linux-watchdog@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-mmc@...r.kernel.org,
linux-gpio@...r.kernel.org,
Alexandre Bailon <abailon@...libre.com>,
Fabien Parent <fparent@...libre.com>,
Amjad Ouled-Ameur <aouledameur@...libre.com>
Subject: Re: [PATCH v3 08/17] arm64: dts: mediatek: add mmc support for mt8365
SoC
On 29/03/2023 15:21, AngeloGioacchino Del Regno wrote:
> Il 29/03/23 10:54, Alexandre Mergnat ha scritto:
>> There are three ports of MSDC (MMC and SD Controller), which are:
>> - MSDC0: EMMC5.1
>> - MSDC1: SD3.0/SDIO3.0
>> - MSDC2: SDIO3.0+
>>
>> Signed-off-by: Alexandre Mergnat <amergnat@...libre.com>
>> ---
>> arch/arm64/boot/dts/mediatek/mt8365.dtsi | 39 ++++++++++++++++++++++++++++++++
>> 1 file changed, 39 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
>> b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
>> index 687011353f69..a67eeca28da5 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
>> @@ -399,6 +399,45 @@ usb_host: usb@...00000 {
>> };
>> };
>> + mmc0: mmc@...30000 {
>> + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
>> + reg = <0 0x11230000 0 0x1000>,
>> + <0 0x11cd0000 0 0x1000>;
>> + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
>> + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
>> + <&infracfg CLK_IFR_MSDC0_HCLK>,
>> + <&infracfg CLK_IFR_MSDC0_SRC>;
>> + clock-names = "source", "hclk", "source_cg";
>> + status = "disabled";
>> + };
>> +
>> + mmc1: mmc@...40000 {
>> + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
>> + reg = <0 0x11240000 0 0x1000>,
>> + <0 0x11c90000 0 0x1000>;
>> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
>> + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
>> + <&infracfg CLK_IFR_MSDC1_HCLK>,
>> + <&infracfg CLK_IFR_MSDC1_SRC>;
>> + clock-names = "source", "hclk", "source_cg";
>> + status = "disabled";
>> + };
>> +
>> + mmc2: mmc@...50000 {
>> + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
>> + reg = <0 0x11250000 0 0x1000>,
>> + <0 0x11c60000 0 0x1000>;
>> + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>;
>> + clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>,
>> + <&infracfg CLK_IFR_MSDC2_HCLK>,
>> + <&infracfg CLK_IFR_MSDC2_SRC>,
>> + <&infracfg CLK_IFR_MSDC2_BK>,
>> + <&infracfg CLK_IFR_AP_MSDC0>;
>> + clock-names = "source", "hclk", "source_cg",
>> + "bus_clk", "sys_cg";
>
> clock-names for this do fit in one 90 columns line.
>
> After compressing it,
>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
>
I applied the patch and dropped you Reviewed-by tag. I think it depends on the
taste of everybody how you prefer to structure this. I've also seen that on
boards you care (mt8183 in that case) there a clocks that don't adhere to the
criteria you mention here ;-)
Anyway many thanks for reviewing this and all the great work in general.
Honestly I feel I didn't made justice by dropping your tag, but as you stated so
explicitly... :)
Regards,
Matthias
Powered by blists - more mailing lists