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Message-Id: <1680243502-23744-5-git-send-email-quic_rohiagar@quicinc.com>
Date: Fri, 31 Mar 2023 11:48:21 +0530
From: Rohit Agarwal <quic_rohiagar@...cinc.com>
To: agross@...nel.org, andersson@...nel.org, konrad.dybcio@...aro.org,
mani@...nel.org, bhelgaas@...gle.com, lpieralisi@...nel.org,
kw@...ux.com, robh@...nel.org, krzysztof.kozlowski+dt@...aro.org,
manivannan.sadhasivam@...aro.org
Cc: linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Rohit Agarwal <quic_rohiagar@...cinc.com>
Subject: [PATCH v5 4/5] ARM: dts: qcom: sdx65-mtp: Enable PCIe PHY
Enable PCIe PHY on SDX65 MTP for PCIe EP. While at it,
updating status as last property for each node.
Signed-off-by: Rohit Agarwal <quic_rohiagar@...cinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
---
arch/arm/boot/dts/qcom-sdx65-mtp.dts | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
index ed98c83..70720e6 100644
--- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
+++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
@@ -245,6 +245,13 @@
status = "okay";
};
+&pcie_phy {
+ vdda-phy-supply = <&vreg_l1b_1p2>;
+ vdda-pll-supply = <&vreg_l4b_0p88>;
+
+ status = "okay";
+};
+
&qpic_bam {
status = "okay";
};
@@ -265,8 +272,9 @@
};
&remoteproc_mpss {
- status = "okay";
memory-region = <&mpss_adsp_mem>;
+
+ status = "okay";
};
&usb {
@@ -278,14 +286,16 @@
};
&usb_hsphy {
- status = "okay";
vdda-pll-supply = <&vreg_l4b_0p88>;
vdda33-supply = <&vreg_l10b_3p08>;
vdda18-supply = <&vreg_l5b_1p8>;
+
+ status = "okay";
};
&usb_qmpphy {
- status = "okay";
vdda-phy-supply = <&vreg_l4b_0p88>;
vdda-pll-supply = <&vreg_l1b_1p2>;
+
+ status = "okay";
};
--
2.7.4
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