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Message-Id: <20230331071642.2483199-1-peng.fan@oss.nxp.com>
Date: Fri, 31 Mar 2023 15:16:42 +0800
From: "Peng Fan (OSS)" <peng.fan@....nxp.com>
To: abelvesa@...nel.org, abel.vesa@...aro.org, mturquette@...libre.com,
sboyd@...nel.org, shawnguo@...nel.org, s.hauer@...gutronix.de,
kernel@...gutronix.de, festevam@...il.com
Cc: linux-imx@....com, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Jacky Bai <ping.bai@....com>, Peng Fan <peng.fan@....com>
Subject: [PATCH] clk: imx: composite-7ulp: Add some delay before deassert the reset
From: Jacky Bai <ping.bai@....com>
Some of the PCCs on i.MX8ULP have a sw_rst bit to control
the peripheral reset through SW method. For peripherals like GPU
that need sync reset, some delay is necessary befere & after release
the reset to make sure the HW is reset into known status. So add
some delay before & after release reset.
This change will not impact i.MX7ULP function
Reviewed-by: Peng Fan <peng.fan@....com>
Signed-off-by: Jacky Bai <ping.bai@....com>
Signed-off-by: Peng Fan <peng.fan@....com>
---
drivers/clk/imx/clk-composite-7ulp.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/clk/imx/clk-composite-7ulp.c b/drivers/clk/imx/clk-composite-7ulp.c
index 4eedd45dbaa8..f9fe968bd900 100644
--- a/drivers/clk/imx/clk-composite-7ulp.c
+++ b/drivers/clk/imx/clk-composite-7ulp.c
@@ -7,6 +7,7 @@
#include <linux/bits.h>
#include <linux/clk-provider.h>
+#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/slab.h>
@@ -37,6 +38,9 @@ static int pcc_gate_enable(struct clk_hw *hw)
if (ret)
return ret;
+ /* wait before release reset */
+ udelay(1);
+
spin_lock_irqsave(gate->lock, flags);
/*
* release the sw reset for peripherals associated with
@@ -48,6 +52,9 @@ static int pcc_gate_enable(struct clk_hw *hw)
spin_unlock_irqrestore(gate->lock, flags);
+ /* wait sync reset done */
+ udelay(1);
+
return 0;
}
--
2.37.1
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