linux-kernel - Re: [PATCH 1/2] phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J784S4

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Message-ID: <cfcdb25b-5426-2532-ab8c-224a5e33baf3@kernel.org>
Date:   Fri, 31 Mar 2023 10:45:00 +0300
From:   Roger Quadros <rogerq@...nel.org>
To:     Siddharth Vadapalli <s-vadapalli@...com>, vkoul@...nel.org,
        kishon@...nel.org
Cc:     linux-phy@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, srk@...com
Subject: Re: [PATCH 1/2] phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in
 J784S4



On 31/03/2023 09:25, Siddharth Vadapalli wrote:
> Each of the CPSW9G ports in TI's J784S4 SoC support modes such as QSGMII.
> 
> Add a new compatible for it and allow the usage of "ti,qsgmii-main-ports"
> property for J784S4.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@...com>
> ---
>  drivers/phy/ti/phy-gmii-sel.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
> index c87118cb2af9..fba5c0c0771c 100644
> --- a/drivers/phy/ti/phy-gmii-sel.c
> +++ b/drivers/phy/ti/phy-gmii-sel.c
> @@ -235,6 +235,15 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = {
>  	.num_qsgmii_main_ports = 2,
>  };
>  
> +static const
> +struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = {

Please make it into one line

> +	.use_of_data = true,
> +	.regfields = phy_gmii_sel_fields_am654,
> +	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
> +	.num_ports = 8,
> +	.num_qsgmii_main_ports = 2,
> +};
> +
>  static const struct of_device_id phy_gmii_sel_id_table[] = {
>  	{
>  		.compatible	= "ti,am3352-phy-gmii-sel",
> @@ -264,6 +273,10 @@ static const struct of_device_id phy_gmii_sel_id_table[] = {
>  		.compatible	= "ti,j721e-cpsw9g-phy-gmii-sel",
>  		.data		= &phy_gmii_sel_cpsw9g_soc_j721e,
>  	},
> +	{
> +		.compatible	= "ti,j784s4-cpsw9g-phy-gmii-sel",
> +		.data		= &phy_gmii_sel_cpsw9g_soc_j784s4,
> +	},
>  	{}
>  };
>  MODULE_DEVICE_TABLE(of, phy_gmii_sel_id_table);
--
cheers,
-roger